6cf7cc6e4d
Switch eventtimers(9) from using struct bintime to sbintime_t. Even before this not a single driver really supported full dynamic range of struct bintime even in theory, not speaking about practical inexpediency. This change legitimates the status quo and cleans up the code.
378 lines
9.3 KiB
C
378 lines
9.3 KiB
C
/*-
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* Copyright (c) 2006-2007 Bruce M. Simpson.
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* Copyright (c) 2003-2004 Juli Mallett.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Simple driver for the 32-bit interval counter built in to all
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* MIPS32 CPUs.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/power.h>
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#include <sys/smp.h>
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#include <sys/time.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <machine/hwfunc.h>
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#include <machine/clock.h>
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#include <machine/locore.h>
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#include <machine/md_var.h>
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#include <machine/intr_machdep.h>
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#include <mips/rmi/interrupt.h>
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uint64_t counter_freq;
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struct timecounter *platform_timecounter;
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static DPCPU_DEFINE(uint32_t, cycles_per_tick);
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static uint32_t cycles_per_usec;
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static DPCPU_DEFINE(volatile uint32_t, counter_upper);
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static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
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static DPCPU_DEFINE(uint32_t, compare_ticks);
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static DPCPU_DEFINE(uint32_t, lost_ticks);
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struct clock_softc {
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int intr_rid;
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struct resource *intr_res;
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void *intr_handler;
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struct timecounter tc;
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struct eventtimer et;
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};
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static struct clock_softc *softc;
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/*
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* Device methods
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*/
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static int clock_probe(device_t);
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static void clock_identify(driver_t *, device_t);
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static int clock_attach(device_t);
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static unsigned counter_get_timecount(struct timecounter *tc);
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void
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mips_timer_early_init(uint64_t clock_hz)
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{
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/* Initialize clock early so that we can use DELAY sooner */
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counter_freq = clock_hz;
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cycles_per_usec = (clock_hz / (1000 * 1000));
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}
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void
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platform_initclocks(void)
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{
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if (platform_timecounter != NULL)
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tc_init(platform_timecounter);
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}
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static uint64_t
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tick_ticker(void)
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{
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uint64_t ret;
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uint32_t ticktock;
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uint32_t t_lower_last, t_upper;
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/*
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* Disable preemption because we are working with cpu specific data.
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*/
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critical_enter();
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/*
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* Note that even though preemption is disabled, interrupts are
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* still enabled. In particular there is a race with clock_intr()
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* reading the values of 'counter_upper' and 'counter_lower_last'.
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*
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* XXX this depends on clock_intr() being executed periodically
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* so that 'counter_upper' and 'counter_lower_last' are not stale.
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*/
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do {
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t_upper = DPCPU_GET(counter_upper);
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t_lower_last = DPCPU_GET(counter_lower_last);
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} while (t_upper != DPCPU_GET(counter_upper));
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ticktock = mips_rd_count();
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critical_exit();
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/* COUNT register wrapped around */
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if (ticktock < t_lower_last)
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t_upper++;
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ret = ((uint64_t)t_upper << 32) | ticktock;
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return (ret);
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}
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void
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mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
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{
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/*
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* XXX: Do not use printf here: uart code 8250 may use DELAY so this
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* function should be called before cninit.
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*/
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counter_freq = platform_counter_freq;
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/*
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* XXX: Some MIPS32 cores update the Count register only every two
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* pipeline cycles.
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* We know this because of status registers in CP0, make it automatic.
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*/
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if (double_count != 0)
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counter_freq /= 2;
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cycles_per_usec = counter_freq / (1 * 1000 * 1000);
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set_cputicker(tick_ticker, counter_freq, 1);
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}
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static int
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sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
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{
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int error;
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uint64_t freq;
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if (softc == NULL)
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return (EOPNOTSUPP);
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freq = counter_freq;
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error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
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if (error == 0 && req->newptr != NULL) {
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counter_freq = freq;
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softc->et.et_frequency = counter_freq;
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softc->tc.tc_frequency = counter_freq;
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}
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return (error);
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}
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SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
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NULL, 0, sysctl_machdep_counter_freq, "QU",
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"Timecounter frequency in Hz");
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static unsigned
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counter_get_timecount(struct timecounter *tc)
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{
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return (mips_rd_count());
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}
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/*
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* Wait for about n microseconds (at least!).
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*/
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void
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DELAY(int n)
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{
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uint32_t cur, last, delta, usecs;
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/*
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* This works by polling the timer and counting the number of
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* microseconds that go by.
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*/
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last = mips_rd_count();
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delta = usecs = 0;
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while (n > usecs) {
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cur = mips_rd_count();
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/* Check to see if the timer has wrapped around. */
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if (cur < last)
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delta += cur + (0xffffffff - last) + 1;
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else
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delta += cur - last;
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last = cur;
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if (delta >= cycles_per_usec) {
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usecs += delta / cycles_per_usec;
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delta %= cycles_per_usec;
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}
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}
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}
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static int
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clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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uint32_t fdiv, div, next;
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if (period != 0)
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div = (et->et_frequency * period) >> 32;
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else
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div = 0;
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if (first != 0)
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fdiv = (et->et_frequency * first) >> 32;
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else
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fdiv = div;
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DPCPU_SET(cycles_per_tick, div);
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next = mips_rd_count() + fdiv;
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DPCPU_SET(compare_ticks, next);
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mips_wr_compare(next);
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return (0);
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}
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static int
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clock_stop(struct eventtimer *et)
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{
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DPCPU_SET(cycles_per_tick, 0);
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mips_wr_compare(0xffffffff);
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return (0);
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}
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/*
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* Device section of file below
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*/
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static int
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clock_intr(void *arg)
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{
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struct clock_softc *sc = (struct clock_softc *)arg;
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uint32_t cycles_per_tick;
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uint32_t count, compare_last, compare_next, lost_ticks;
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cycles_per_tick = DPCPU_GET(cycles_per_tick);
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/*
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* Set next clock edge.
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*/
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count = mips_rd_count();
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compare_last = DPCPU_GET(compare_ticks);
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if (cycles_per_tick > 0) {
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compare_next = count + cycles_per_tick;
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DPCPU_SET(compare_ticks, compare_next);
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mips_wr_compare(compare_next);
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} else /* In one-shot mode timer should be stopped after the event. */
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mips_wr_compare(0xffffffff);
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/* COUNT register wrapped around */
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if (count < DPCPU_GET(counter_lower_last)) {
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DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
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}
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DPCPU_SET(counter_lower_last, count);
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if (cycles_per_tick > 0) {
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/*
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* Account for the "lost time" between when the timer interrupt
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* fired and when 'clock_intr' actually started executing.
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*/
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lost_ticks = DPCPU_GET(lost_ticks);
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lost_ticks += count - compare_last;
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/*
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* If the COUNT and COMPARE registers are no longer in sync
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* then make up some reasonable value for the 'lost_ticks'.
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*
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* This could happen, for e.g., after we resume normal
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* operations after exiting the debugger.
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*/
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if (lost_ticks > 2 * cycles_per_tick)
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lost_ticks = cycles_per_tick;
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while (lost_ticks >= cycles_per_tick) {
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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lost_ticks -= cycles_per_tick;
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}
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DPCPU_SET(lost_ticks, lost_ticks);
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}
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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static int
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clock_probe(device_t dev)
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{
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if (device_get_unit(dev) != 0)
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panic("can't attach more clocks");
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device_set_desc(dev, "Generic MIPS32 ticker");
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return (0);
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}
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static void
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clock_identify(driver_t * drv, device_t parent)
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{
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BUS_ADD_CHILD(parent, 0, "clock", 0);
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}
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static int
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clock_attach(device_t dev)
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{
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struct clock_softc *sc;
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softc = sc = device_get_softc(dev);
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cpu_establish_hardintr("compare", clock_intr, NULL,
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sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
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sc->tc.tc_get_timecount = counter_get_timecount;
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sc->tc.tc_counter_mask = 0xffffffff;
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sc->tc.tc_frequency = counter_freq;
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sc->tc.tc_name = "MIPS32";
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sc->tc.tc_quality = 800;
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sc->tc.tc_priv = sc;
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tc_init(&sc->tc);
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sc->et.et_name = "MIPS32";
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sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
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ET_FLAGS_PERCPU;
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sc->et.et_quality = 800;
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sc->et.et_frequency = counter_freq;
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sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = clock_start;
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sc->et.et_stop = clock_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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return (0);
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}
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static device_method_t clock_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, clock_probe),
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DEVMETHOD(device_identify, clock_identify),
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DEVMETHOD(device_attach, clock_attach),
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DEVMETHOD(device_detach, bus_generic_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{0, 0}
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};
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static driver_t clock_driver = {
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"clock",
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clock_methods,
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sizeof(struct clock_softc),
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};
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static devclass_t clock_devclass;
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DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
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