3a6a9a3bcc
from the git tree. This merges a lot that we're not using, but there's too many files to be selective and have a hope of catching everything. If there are conflicts with the rest of the tree, we'll resolve them on a case by case basis. MFC after: 2 weeks Sponsored by: Netflix, Inc.
250 lines
5.4 KiB
Plaintext
250 lines
5.4 KiB
Plaintext
/*
|
|
* Copyright (C) 2011 Picochip, Jamie Iles
|
|
*
|
|
* This software is licensed under the terms of the GNU General Public
|
|
* License version 2, as published by the Free Software Foundation, and
|
|
* may be copied, distributed, and modified under those terms.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
/include/ "skeleton.dtsi"
|
|
/ {
|
|
model = "Picochip picoXcell PC3X2";
|
|
compatible = "picochip,pc3x2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cpus {
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
|
|
cpu {
|
|
compatible = "arm,arm1176jz-s";
|
|
device_type = "cpu";
|
|
clock-frequency = <400000000>;
|
|
d-cache-line-size = <32>;
|
|
d-cache-size = <32768>;
|
|
i-cache-line-size = <32>;
|
|
i-cache-size = <32768>;
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pclk: clock@0 {
|
|
compatible = "fixed-clock";
|
|
clock-outputs = "bus", "pclk";
|
|
clock-frequency = <200000000>;
|
|
ref-clock = <&ref_clk>, "ref";
|
|
};
|
|
};
|
|
|
|
paxi {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x80000000 0x400000>;
|
|
|
|
emac: gem@30000 {
|
|
compatible = "cadence,gem";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <31>;
|
|
};
|
|
|
|
dmac1: dmac@40000 {
|
|
compatible = "snps,dw-dmac";
|
|
reg = <0x40000 0x10000>;
|
|
interrupts = <25>;
|
|
};
|
|
|
|
dmac2: dmac@50000 {
|
|
compatible = "snps,dw-dmac";
|
|
reg = <0x50000 0x10000>;
|
|
interrupts = <26>;
|
|
};
|
|
|
|
vic0: interrupt-controller@60000 {
|
|
compatible = "arm,pl192-vic";
|
|
interrupt-controller;
|
|
reg = <0x60000 0x1000>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
vic1: interrupt-controller@64000 {
|
|
compatible = "arm,pl192-vic";
|
|
interrupt-controller;
|
|
reg = <0x64000 0x1000>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
fuse: picoxcell-fuse@80000 {
|
|
compatible = "picoxcell,fuse-pc3x2";
|
|
reg = <0x80000 0x10000>;
|
|
};
|
|
|
|
ssi: picoxcell-spi@90000 {
|
|
compatible = "picoxcell,spi";
|
|
reg = <0x90000 0x10000>;
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <10>;
|
|
};
|
|
|
|
ipsec: spacc@100000 {
|
|
compatible = "picochip,spacc-ipsec";
|
|
reg = <0x100000 0x10000>;
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <24>;
|
|
ref-clock = <&pclk>, "ref";
|
|
};
|
|
|
|
srtp: spacc@140000 {
|
|
compatible = "picochip,spacc-srtp";
|
|
reg = <0x140000 0x10000>;
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <23>;
|
|
};
|
|
|
|
l2_engine: spacc@180000 {
|
|
compatible = "picochip,spacc-l2";
|
|
reg = <0x180000 0x10000>;
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <22>;
|
|
ref-clock = <&pclk>, "ref";
|
|
};
|
|
|
|
apb {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x200000 0x80000>;
|
|
|
|
rtc0: rtc@00000 {
|
|
compatible = "picochip,pc3x2-rtc";
|
|
clock-freq = <200000000>;
|
|
reg = <0x00000 0xf>;
|
|
interrupt-parent = <&vic1>;
|
|
interrupts = <8>;
|
|
};
|
|
|
|
timer0: timer@10000 {
|
|
compatible = "picochip,pc3x2-timer";
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <4>;
|
|
clock-freq = <200000000>;
|
|
reg = <0x10000 0x14>;
|
|
};
|
|
|
|
timer1: timer@10014 {
|
|
compatible = "picochip,pc3x2-timer";
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <5>;
|
|
clock-freq = <200000000>;
|
|
reg = <0x10014 0x14>;
|
|
};
|
|
|
|
timer2: timer@10028 {
|
|
compatible = "picochip,pc3x2-timer";
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <6>;
|
|
clock-freq = <200000000>;
|
|
reg = <0x10028 0x14>;
|
|
};
|
|
|
|
timer3: timer@1003c {
|
|
compatible = "picochip,pc3x2-timer";
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <7>;
|
|
clock-freq = <200000000>;
|
|
reg = <0x1003c 0x14>;
|
|
};
|
|
|
|
gpio: gpio@20000 {
|
|
compatible = "snps,dw-apb-gpio";
|
|
reg = <0x20000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg-io-width = <4>;
|
|
|
|
banka: gpio-controller@0 {
|
|
compatible = "snps,dw-apb-gpio-bank";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-generic,nr-gpio = <8>;
|
|
|
|
regoffset-dat = <0x50>;
|
|
regoffset-set = <0x00>;
|
|
regoffset-dirout = <0x04>;
|
|
};
|
|
|
|
bankb: gpio-controller@1 {
|
|
compatible = "snps,dw-apb-gpio-bank";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-generic,nr-gpio = <8>;
|
|
|
|
regoffset-dat = <0x54>;
|
|
regoffset-set = <0x0c>;
|
|
regoffset-dirout = <0x10>;
|
|
};
|
|
};
|
|
|
|
uart0: uart@30000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x30000 0x1000>;
|
|
interrupt-parent = <&vic1>;
|
|
interrupts = <10>;
|
|
clock-frequency = <3686400>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
};
|
|
|
|
uart1: uart@40000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x40000 0x1000>;
|
|
interrupt-parent = <&vic1>;
|
|
interrupts = <9>;
|
|
clock-frequency = <3686400>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
};
|
|
|
|
wdog: watchdog@50000 {
|
|
compatible = "snps,dw-apb-wdg";
|
|
reg = <0x50000 0x10000>;
|
|
interrupt-parent = <&vic0>;
|
|
interrupts = <11>;
|
|
bus-clock = <&pclk>, "bus";
|
|
};
|
|
};
|
|
};
|
|
|
|
rwid-axi {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
ebi@50000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x40000000 0x08000000
|
|
1 0 0x48000000 0x08000000
|
|
2 0 0x50000000 0x08000000
|
|
3 0 0x58000000 0x08000000>;
|
|
};
|
|
|
|
axi2pico@c0000000 {
|
|
compatible = "picochip,axi2pico-pc3x2";
|
|
reg = <0xc0000000 0x10000>;
|
|
interrupts = <13 14 15 16 17 18 19 20 21>;
|
|
};
|
|
};
|
|
};
|