2668945977
now uave a full copy of the arm device tree sources to help when adding support for newer boards. Sponsored by: ABT Systems Ltd
137 lines
3.8 KiB
Plaintext
137 lines
3.8 KiB
Plaintext
/*
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* Copyright (C) 2015 STMicroelectronics Limited.
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* Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih407-clock.dtsi"
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#include "stih407-family.dtsi"
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/ {
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soc {
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sti-display-subsystem {
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compatible = "st,sti-display-subsystem";
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#address-cells = <1>;
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#size-cells = <1>;
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assigned-clocks = <&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_GDP1>,
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<&clk_s_d2_flexgen CLK_PIX_GDP2>,
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<&clk_s_d2_flexgen CLK_PIX_GDP3>,
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<&clk_s_d2_flexgen CLK_PIX_GDP4>;
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assigned-clock-parents = <0>,
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<0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>;
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assigned-clock-rates = <297000000>, <297000000>;
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ranges;
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sti-compositor@9d11000 {
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compatible = "st,stih407-compositor";
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reg = <0x9d11000 0x1000>;
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clock-names = "compo_main",
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"compo_aux",
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"pix_main",
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"pix_aux",
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"pix_gdp1",
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"pix_gdp2",
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"pix_gdp3",
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"pix_gdp4",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
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<&clk_s_c0_flexgen CLK_COMPO_DVP>,
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<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_GDP1>,
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<&clk_s_d2_flexgen CLK_PIX_GDP2>,
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<&clk_s_d2_flexgen CLK_PIX_GDP3>,
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<&clk_s_d2_flexgen CLK_PIX_GDP4>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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reset-names = "compo-main", "compo-aux";
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resets = <&softreset STIH407_COMPO_SOFTRESET>,
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<&softreset STIH407_COMPO_SOFTRESET>;
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st,vtg = <&vtg_main>, <&vtg_aux>;
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};
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sti-tvout@8d08000 {
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compatible = "st,stih407-tvout";
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reg = <0x8d08000 0x1000>;
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reg-names = "tvout-reg";
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reset-names = "tvout";
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resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
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#address-cells = <1>;
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#size-cells = <1>;
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assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
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<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
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<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
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<&clk_s_d0_flexgen CLK_PCM_0>,
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<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
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<&clk_s_d2_flexgen CLK_HDDAC>;
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assigned-clock-parents = <&clk_s_d2_quadfs 0>,
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<&clk_tmdsout_hdmi>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d0_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>;
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};
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sti-hdmi@8d04000 {
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compatible = "st,stih407-hdmi";
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reg = <0x8d04000 0x1000>;
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reg-names = "hdmi-reg";
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interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
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interrupt-names = "irq";
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clock-names = "pix",
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"tmds",
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"phy",
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"audio",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
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<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
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<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
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<&clk_s_d0_flexgen CLK_PCM_0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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hdmi,hpd-gpio = <&pio5 3>;
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reset-names = "hdmi";
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resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
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ddc = <&hdmiddc>;
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};
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sti-hda@8d02000 {
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compatible = "st,stih407-hda";
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reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
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reg-names = "hda-reg", "video-dacs-ctrl";
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clock-names = "pix",
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"hddac",
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"main_parent",
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"aux_parent";
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clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
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<&clk_s_d2_flexgen CLK_HDDAC>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>;
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};
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};
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};
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};
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