2668945977
now uave a full copy of the arm device tree sources to help when adding support for newer boards. Sponsored by: ABT Systems Ltd
140 lines
3.1 KiB
Plaintext
140 lines
3.1 KiB
Plaintext
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/zx296702-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "zte,zx296702-smp";
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2cc>;
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2cc>;
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reg = <1>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&intc>;
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ranges;
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matrix: bus-matrix@400000 {
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compatible = "zte,zx-bus-matrix";
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reg = <0x00400000 0x1000>;
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};
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intc: interrupt-controller@00801000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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reg = <0x00801000 0x1000>,
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<0x00800100 0x100>;
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};
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global_timer: timer@008000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x00800200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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clocks = <&topclk ZX296702_A9_PERIPHCLK>;
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};
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l2cc: l2-cache-controller@0x00c00000 {
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compatible = "arm,pl310-cache";
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reg = <0x00c00000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <1 1 1>;
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arm,double-linefill = <1>;
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arm,double-linefill-incr = <0>;
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};
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pcu: pcu@0xa0008000 {
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compatible = "zte,zx296702-pcu";
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reg = <0xa0008000 0x1000>;
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};
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topclk: topclk@0x09800000 {
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compatible = "zte,zx296702-topcrm-clk";
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reg = <0x09800000 0x1000>;
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#clock-cells = <1>;
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};
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lsp1clk: lsp1clk@0x09400000 {
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compatible = "zte,zx296702-lsp1crpm-clk";
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reg = <0x09400000 0x1000>;
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#clock-cells = <1>;
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};
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lsp0clk: lsp0clk@0x0b000000 {
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compatible = "zte,zx296702-lsp0crpm-clk";
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reg = <0x0b000000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@0x09405000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09405000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART0_WCLK>;
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status = "disabled";
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};
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uart1: serial@0x09406000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09406000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART1_WCLK>;
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status = "disabled";
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};
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mmc0: mmc@0x09408000 {
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compatible = "snps,dw-mshc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x09408000 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <32>;
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clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
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<&lsp1clk ZX296702_SDMMC0_WCLK>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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mmc1: mmc@0x0b003000 {
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compatible = "snps,dw-mshc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0b003000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <32>;
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clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
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<&lsp0clk ZX296702_SDMMC1_WCLK>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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sysctrl: sysctrl@0xa0007000 {
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compatible = "zte,sysctrl", "syscon";
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reg = <0xa0007000 0x1000>;
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};
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};
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};
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