179f14534e
This is an import of the reworked LEDE dts files. Besides other things they make it easier for us to reuse. The only diffs left are for the following SoCs: MT7620A (fbsd-mt7620a.dtsi) MT7621 (fbsd-mt7621.dtsi) MT7628 (fbsd-mt7628an.dtsi) RT3883 (fbsd-rt3883.dtsi) So we include the fbsd-*.dtsi files at the end of the original LEDE dtsi files, using '#include "fbsd-xxxx.dtsi"'. For example, for MT7621, the LEDE dtsi file is mt7621.dtsi. At the end of it we add: #include "fbsd-mt7621.dtsi" Approved by: adrian (mentor) Obtained from: LEDE project Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6394
204 lines
3.4 KiB
Plaintext
204 lines
3.4 KiB
Plaintext
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,rt2880-soc";
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cpus {
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cpu@0 {
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compatible = "mips,mips24KEc";
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};
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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aliases {
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serial0 = &uartlite;
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus: palmbus@300000 {
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compatible = "palmbus";
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reg = <0x300000 0x200000>;
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ranges = <0x0 0x300000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: sysc@0 {
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compatible = "ralink,rt2880-sysc";
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reg = <0x000 0x100>;
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};
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timer: timer@100 {
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compatible = "ralink,rt2880-timer";
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reg = <0x100 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <1>;
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status = "disabled";
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};
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watchdog: watchdog@120 {
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compatible = "ralink,rt2880-wdt";
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reg = <0x120 0x10>;
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};
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intc: intc@200 {
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compatible = "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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memc: memc@300 {
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compatible = "ralink,rt2880-memc";
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reg = <0x300 0x100>;
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};
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gpio0: gpio@600 {
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compatible = "ralink,rt2880-gpio";
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reg = <0x600 0x34>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <0>;
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ralink,num-gpios = <24>;
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ralink,register-map = [ 00 04 08 0c
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20 24 28 2c
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30 34 ];
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};
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gpio1: gpio@638 {
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compatible = "ralink,rt2880-gpio";
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reg = <0x638 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <24>;
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ralink,num-gpios = <16>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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gpio2: gpio@660 {
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compatible = "ralink,rt2880-gpio";
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reg = <0x660 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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ralink,gpio-base = <40>;
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ralink,num-gpios = <32>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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uartlite: uartlite@c00 {
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compatible = "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <8>;
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reg-shift = <2>;
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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sdram {
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ralink,group = "sdram";
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ralink,function = "sdram";
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};
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};
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spi_pins: spi {
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spi {
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ralink,group = "spi";
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ralink,function = "spi";
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};
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};
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uartlite_pins: uartlite {
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uart {
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ralink,group = "uartlite";
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ralink,function = "uartlite";
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};
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};
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};
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rstctrl: rstctrl {
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compatible = "ralink,rt2880-reset";
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#reset-cells = <1>;
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};
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clkctrl: clkctrl {
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compatible = "ralink,rt2880-clock";
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#clock-cells = <1>;
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};
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ethernet: ethernet@400000 {
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compatible = "ralink,rt2880-eth";
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reg = <0x00400000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rstctrl 18>;
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reset-names = "fe";
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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status = "disabled";
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port@0 {
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compatible = "ralink,rt2880-port", "mediatek,eth-port";
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reg = <0>;
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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wmac: wmac@480000 {
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compatible = "ralink,rt2880-wmac";
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reg = <0x480000 0x40000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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ralink,eeprom = "soc_wmac.eeprom";
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};
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};
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