ac2071063e
implementations or no implementation on all platforms. Some of these functions might be good ideas, but their semantics were unclear given the lack of implementation, and an unlucky porter could be fooled into trying to implement them or, worse, being baffled when something like platform_trap_enter() failed to be called.
618 lines
15 KiB
C
618 lines
15 KiB
C
/*-
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* Copyright (c) 2006-2009 RMI Corporation
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* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/rtprio.h>
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#include <sys/systm.h>
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#include <sys/interrupt.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/random.h>
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#include <sys/cons.h> /* cinit() */
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <sys/queue.h>
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#include <sys/smp.h>
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#include <sys/timetc.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/asm.h>
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#include <machine/pmap.h>
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#include <machine/trap.h>
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#include <machine/clock.h>
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#include <machine/fls64.h>
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#include <machine/intr_machdep.h>
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#include <machine/smp.h>
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#include <mips/rmi/iomap.h>
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#include <mips/rmi/msgring.h>
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#include <mips/rmi/interrupt.h>
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#include <mips/rmi/pic.h>
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#include <mips/rmi/board.h>
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#include <mips/rmi/rmi_mips_exts.h>
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#include <mips/rmi/rmi_boot_info.h>
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void mpwait(void);
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unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
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/* 4KB static data aread to keep a copy of the bootload env until
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the dynamic kenv is setup */
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char boot1_env[4096];
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int rmi_spin_mutex_safe=0;
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struct mtx xlr_pic_lock;
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/*
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* Parameters from boot loader
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*/
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struct boot1_info xlr_boot1_info;
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int xlr_run_mode;
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int xlr_argc;
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int32_t *xlr_argv, *xlr_envp;
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uint64_t cpu_mask_info;
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uint32_t xlr_online_cpumask;
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uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
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int xlr_shtlb_enabled;
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int xlr_ncores;
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int xlr_threads_per_core;
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uint32_t xlr_hw_thread_mask;
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int xlr_cpuid_to_hwtid[MAXCPU];
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int xlr_hwtid_to_cpuid[MAXCPU];
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static void
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xlr_setup_mmu_split(void)
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{
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uint64_t mmu_setup;
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int val = 0;
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if (xlr_threads_per_core == 4 && xlr_shtlb_enabled == 0)
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return; /* no change from boot setup */
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switch (xlr_threads_per_core) {
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case 1:
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val = 0; break;
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case 2:
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val = 2; break;
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case 4:
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val = 3; break;
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}
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mmu_setup = read_xlr_ctrl_register(4, 0);
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mmu_setup = mmu_setup & ~0x06;
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mmu_setup |= (val << 1);
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/* turn on global mode */
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if (xlr_shtlb_enabled)
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mmu_setup |= 0x01;
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write_xlr_ctrl_register(4, 0, mmu_setup);
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}
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static void
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xlr_parse_mmu_options(void)
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{
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#ifdef notyet
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char *hw_env, *start, *end;
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#endif
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uint32_t cpu_map;
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uint8_t core0_thr_mask, core_thr_mask;
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int i, j, k;
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/* First check for the shared TLB setup */
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xlr_shtlb_enabled = 0;
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#ifdef notyet
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/*
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* We don't support sharing TLB per core - TODO
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*/
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xlr_shtlb_enabled = 0;
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if ((hw_env = getenv("xlr.shtlb")) != NULL) {
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start = hw_env;
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tmp = strtoul(start, &end, 0);
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if (start != end)
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xlr_shtlb_enabled = (tmp != 0);
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else
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printf("Bad value for xlr.shtlb [%s]\n", hw_env);
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freeenv(hw_env);
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}
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#endif
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/*
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* XLR supports splitting the 64 TLB entries across one, two or four
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* threads (split mode). XLR also allows the 64 TLB entries to be shared
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* across all threads in the core using a global flag (shared TLB mode).
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* We will support 1/2/4 threads in split mode or shared mode.
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*
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*/
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xlr_ncores = 1;
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cpu_map = xlr_boot1_info.cpu_online_map;
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#ifndef SMP /* Uniprocessor! */
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if (cpu_map != 0x1) {
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printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
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"WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
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cpu_map = 0x1;
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}
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#endif
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core0_thr_mask = cpu_map & 0xf;
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switch (core0_thr_mask) {
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case 1:
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xlr_threads_per_core = 1; break;
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case 3:
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xlr_threads_per_core = 2; break;
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case 0xf:
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xlr_threads_per_core = 4; break;
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default:
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goto unsupp;
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}
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/* Verify other cores CPU masks */
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for (i = 1; i < XLR_MAX_CORES; i++) {
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core_thr_mask = (cpu_map >> (i*4)) & 0xf;
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if (core_thr_mask) {
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if (core_thr_mask != core0_thr_mask)
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goto unsupp;
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xlr_ncores++;
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}
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}
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xlr_hw_thread_mask = cpu_map;
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/* setup hardware processor id to cpu id mapping */
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for (i = 0; i< MAXCPU; i++)
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xlr_cpuid_to_hwtid[i] =
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xlr_hwtid_to_cpuid [i] = -1;
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for (i = 0, k = 0; i < XLR_MAX_CORES; i++) {
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if (((cpu_map >> (i*4)) & 0xf) == 0)
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continue;
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for (j = 0; j < xlr_threads_per_core; j++) {
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xlr_cpuid_to_hwtid[k] = i*4 + j;
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xlr_hwtid_to_cpuid[i*4 + j] = k;
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k++;
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}
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}
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/* setup for the startup core */
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xlr_setup_mmu_split();
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return;
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unsupp:
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printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
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"\tcore0 thread mask [%lx], boot cpu mask [%lx]\n"
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"\tUsing default, 16 TLB entries per CPU, split mode\n",
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(u_long)core0_thr_mask, (u_long)cpu_map);
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panic("Invalid CPU mask - halting.\n");
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return;
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}
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static void
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xlr_set_boot_flags(void)
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{
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char *p;
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p = getenv("bootflags");
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if (p == NULL)
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p = getenv("boot_flags"); /* old style */
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if (p == NULL)
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return;
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for (; p && *p != '\0'; p++) {
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switch (*p) {
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case 'd':
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case 'D':
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boothowto |= RB_KDB;
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break;
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case 'g':
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case 'G':
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boothowto |= RB_GDB;
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break;
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case 'v':
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case 'V':
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boothowto |= RB_VERBOSE;
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break;
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case 's': /* single-user (default, supported for sanity) */
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case 'S':
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boothowto |= RB_SINGLE;
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break;
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default:
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printf("Unrecognized boot flag '%c'.\n", *p);
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break;
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}
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}
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freeenv(p);
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return;
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}
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extern uint32_t _end;
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static void
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mips_init(void)
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{
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init_param1();
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init_param2(physmem);
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mips_cpu_init();
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cpuinfo.cache_coherent_dma = TRUE;
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pmap_bootstrap();
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#ifdef DDB
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kdb_init();
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if (boothowto & RB_KDB) {
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kdb_enter("Boot flags requested debugger", NULL);
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}
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#endif
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mips_proc0_init();
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mutex_init();
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}
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u_int
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platform_get_timecount(struct timecounter *tc __unused)
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{
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return (0xffffffffU - pic_timer_count32(PIC_CLOCK_TIMER));
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}
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static void
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xlr_pic_init(void)
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{
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struct timecounter pic_timecounter = {
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platform_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0U, /* counter_mask */
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PIC_TIMER_HZ, /* frequency */
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"XLRPIC", /* name */
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2000, /* quality (adjusted in code) */
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};
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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int i, irq;
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write_c0_eimr64(0ULL);
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mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
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xlr_write_reg(mmio, PIC_CTRL, 0);
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/* Initialize all IRT entries */
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for (i = 0; i < PIC_NUM_IRTS; i++) {
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irq = PIC_INTR_TO_IRQ(i);
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/*
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* Disable all IRTs. Set defaults (local scheduling, high
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* polarity, level * triggered, and CPU irq)
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*/
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xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq);
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/* Bind all PIC irqs to cpu 0 */
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xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
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}
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/* Setup timer 7 of PIC as a timestamp, no interrupts */
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pic_init_timer(PIC_CLOCK_TIMER);
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pic_set_timer(PIC_CLOCK_TIMER, ~UINT64_C(0));
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platform_timecounter = &pic_timecounter;
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}
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static void
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xlr_mem_init(void)
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{
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struct xlr_boot1_mem_map *boot_map;
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vm_size_t physsz = 0;
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int i, j;
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/* get physical memory info from boot loader */
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boot_map = (struct xlr_boot1_mem_map *)
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(unsigned long)xlr_boot1_info.psb_mem_map;
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for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) {
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if (boot_map->physmem_map[i].type != BOOT1_MEM_RAM)
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continue;
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if (j == 14) {
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printf("*** ERROR *** memory map too large ***\n");
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break;
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}
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if (j == 0) {
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/* start after kernel end */
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phys_avail[0] = (vm_paddr_t)
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MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
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/* boot loader start */
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/* HACK to Use bootloaders memory region */
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if (boot_map->physmem_map[0].size == 0x0c000000) {
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boot_map->physmem_map[0].size = 0x0ff00000;
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}
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phys_avail[1] = boot_map->physmem_map[0].addr +
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boot_map->physmem_map[0].size;
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printf("First segment: addr:%#jx -> %#jx \n",
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(uintmax_t)phys_avail[0],
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(uintmax_t)phys_avail[1]);
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dump_avail[0] = phys_avail[0];
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dump_avail[1] = phys_avail[1];
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} else {
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#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
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/*
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* In 32 bit physical address mode we cannot use
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* mem > 0xffffffff
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*/
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if (boot_map->physmem_map[i].addr > 0xfffff000U) {
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printf("Memory: start %#jx size %#jx ignored"
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"(>4GB)\n",
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(intmax_t)boot_map->physmem_map[i].addr,
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(intmax_t)boot_map->physmem_map[i].size);
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continue;
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}
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if (boot_map->physmem_map[i].addr +
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boot_map->physmem_map[i].size > 0xfffff000U) {
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boot_map->physmem_map[i].size = 0xfffff000U -
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boot_map->physmem_map[i].addr;
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printf("Memory: start %#jx limited to 4GB\n",
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(intmax_t)boot_map->physmem_map[i].addr);
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}
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#endif /* !PHYSADDR_64_BIT */
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phys_avail[j] = (vm_paddr_t)
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boot_map->physmem_map[i].addr;
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phys_avail[j + 1] = phys_avail[j] +
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boot_map->physmem_map[i].size;
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printf("Next segment : addr:%#jx -> %#jx\n",
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(uintmax_t)phys_avail[j],
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(uintmax_t)phys_avail[j+1]);
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}
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dump_avail[j] = phys_avail[j];
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dump_avail[j+1] = phys_avail[j+1];
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physsz += boot_map->physmem_map[i].size;
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}
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phys_avail[j] = phys_avail[j + 1] = 0;
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realmem = physmem = btoc(physsz);
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}
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void
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platform_start(__register_t a0 __unused,
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__register_t a1 __unused,
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__register_t a2 __unused,
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__register_t a3 __unused)
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{
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int i;
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#ifdef SMP
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uint32_t tmp;
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void (*wakeup) (void *, void *, unsigned int);
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#endif
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/* Save boot loader and other stuff from scratch regs */
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xlr_boot1_info = *(struct boot1_info *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
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cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
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xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2);
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xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3);
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xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4);
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/*
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* argv and envp are passed in array of 32bit pointers
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*/
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xlr_argv = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5);
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xlr_envp = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6);
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/* Initialize pcpu stuff */
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mips_pcpu0_init();
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/* initialize console so that we have printf */
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boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
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/* clockrate used by delay, so initialize it here */
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cpu_clock = xlr_boot1_info.cpu_frequency / 1000000;
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/*
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* Note the time counter on CPU0 runs not at system clock speed, but
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* at PIC time counter speed (which is returned by
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* platform_get_frequency(). Thus we do not use
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* xlr_boot1_info.cpu_frequency here.
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*/
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mips_timer_early_init(xlr_boot1_info.cpu_frequency);
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/* Init console please */
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cninit();
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init_static_kenv(boot1_env, sizeof(boot1_env));
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printf("Environment (from %d args):\n", xlr_argc - 1);
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if (xlr_argc == 1)
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printf("\tNone\n");
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for (i = 1; i < xlr_argc; i++) {
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char *n, *arg;
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arg = (char *)(intptr_t)xlr_argv[i];
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printf("\t%s\n", arg);
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n = strsep(&arg, "=");
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if (arg == NULL)
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setenv(n, "1");
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else
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setenv(n, arg);
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}
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xlr_set_boot_flags();
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xlr_parse_mmu_options();
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xlr_mem_init();
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/* Set up hz, among others. */
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mips_init();
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#ifdef SMP
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/*
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* If thread 0 of any core is not available then mark whole core as
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* not available
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*/
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tmp = xlr_boot1_info.cpu_online_map;
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for (i = 4; i < MAXCPU; i += 4) {
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if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
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/*
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* Oops.. thread 0 is not available. Disable whole
|
|
* core
|
|
*/
|
|
tmp = tmp & ~(0xf << i);
|
|
printf("WARNING: Core %d is disabled because thread 0"
|
|
" of this core is not enabled.\n", i / 4);
|
|
}
|
|
}
|
|
xlr_boot1_info.cpu_online_map = tmp;
|
|
|
|
/* Wakeup Other cpus, and put them in bsd park code. */
|
|
wakeup = ((void (*) (void *, void *, unsigned int))
|
|
(unsigned long)(xlr_boot1_info.wakeup));
|
|
printf("Waking up CPUs 0x%jx.\n",
|
|
(intmax_t)xlr_boot1_info.cpu_online_map & ~(0x1U));
|
|
if (xlr_boot1_info.cpu_online_map & ~(0x1U))
|
|
wakeup(mpwait, 0,
|
|
(unsigned int)xlr_boot1_info.cpu_online_map);
|
|
#endif
|
|
|
|
/* xlr specific post initialization */
|
|
/* initialize other on chip stuff */
|
|
xlr_board_info_setup();
|
|
xlr_msgring_config();
|
|
xlr_pic_init();
|
|
xlr_msgring_cpu_init();
|
|
|
|
mips_timer_init_params(xlr_boot1_info.cpu_frequency, 0);
|
|
|
|
printf("Platform specific startup now completes\n");
|
|
}
|
|
|
|
void
|
|
platform_cpu_init()
|
|
{
|
|
}
|
|
|
|
void
|
|
platform_reset(void)
|
|
{
|
|
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
|
|
|
|
/* write 1 to GPIO software reset register */
|
|
xlr_write_reg(mmio, 8, 1);
|
|
}
|
|
|
|
#ifdef SMP
|
|
int xlr_ap_release[MAXCPU];
|
|
|
|
int
|
|
platform_start_ap(int cpuid)
|
|
{
|
|
int hwid = xlr_cpuid_to_hwtid[cpuid];
|
|
|
|
if (xlr_boot1_info.cpu_online_map & (1<<hwid)) {
|
|
/*
|
|
* other cpus are enabled by the boot loader and they will be
|
|
* already looping in mpwait, release them
|
|
*/
|
|
atomic_store_rel_int(&xlr_ap_release[hwid], 1);
|
|
return (0);
|
|
} else
|
|
return (-1);
|
|
}
|
|
|
|
void
|
|
platform_init_ap(int cpuid)
|
|
{
|
|
uint32_t stat;
|
|
|
|
/* The first thread has to setup the core MMU split */
|
|
if (xlr_thr_id() == 0)
|
|
xlr_setup_mmu_split();
|
|
|
|
/* Setup interrupts for secondary CPUs here */
|
|
stat = mips_rd_status();
|
|
KASSERT((stat & MIPS_SR_INT_IE) == 0,
|
|
("Interrupts enabled in %s!", __func__));
|
|
stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
|
|
mips_wr_status(stat);
|
|
|
|
write_c0_eimr64(0ULL);
|
|
xlr_enable_irq(IRQ_IPI);
|
|
xlr_enable_irq(IRQ_TIMER);
|
|
if (xlr_thr_id() == 0)
|
|
xlr_msgring_cpu_init();
|
|
xlr_enable_irq(IRQ_MSGRING);
|
|
|
|
return;
|
|
}
|
|
|
|
int
|
|
platform_ipi_intrnum(void)
|
|
{
|
|
|
|
return (IRQ_IPI);
|
|
}
|
|
|
|
void
|
|
platform_ipi_send(int cpuid)
|
|
{
|
|
|
|
pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_intrnum());
|
|
}
|
|
|
|
void
|
|
platform_ipi_clear(void)
|
|
{
|
|
}
|
|
|
|
int
|
|
platform_processor_id(void)
|
|
{
|
|
|
|
return (xlr_hwtid_to_cpuid[xlr_cpu_id()]);
|
|
}
|
|
|
|
void
|
|
platform_cpu_mask(cpuset_t *mask)
|
|
{
|
|
int i, s;
|
|
|
|
CPU_ZERO(mask);
|
|
s = xlr_ncores * xlr_threads_per_core;
|
|
for (i = 0; i < s; i++)
|
|
CPU_SET(i, mask);
|
|
}
|
|
|
|
struct cpu_group *
|
|
platform_smp_topo()
|
|
{
|
|
|
|
return (smp_topo_2level(CG_SHARE_L2, xlr_ncores, CG_SHARE_L1,
|
|
xlr_threads_per_core, CG_FLAG_THREAD));
|
|
}
|
|
#endif
|