352e51d169
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
68 lines
3.2 KiB
C
68 lines
3.2 KiB
C
/* $NetBSD: cache_mipsNN.h,v 1.4 2003/02/17 11:35:02 simonb Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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void mipsNN_cache_init(struct mips_cpuinfo *);
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void mipsNN_icache_sync_all_16(void);
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void mipsNN_icache_sync_all_32(void);
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void mipsNN_icache_sync_range_16(vm_offset_t, vm_size_t);
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void mipsNN_icache_sync_range_32(vm_offset_t, vm_size_t);
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void mipsNN_icache_sync_range_index_16(vm_offset_t, vm_size_t);
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void mipsNN_icache_sync_range_index_32(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wbinv_all_16(void);
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void mipsNN_pdcache_wbinv_all_32(void);
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void mipsNN_pdcache_wbinv_range_16(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wbinv_range_32(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wbinv_range_index_16(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wbinv_range_index_32(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_inv_range_16(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_inv_range_32(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wb_range_16(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wb_range_32(vm_offset_t, vm_size_t);
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#ifdef TARGET_OCTEON
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void mipsNN_icache_sync_all_128(void);
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void mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t);
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void mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wbinv_all_128(void);
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void mipsNN_pdcache_wbinv_range_128(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t);
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void mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t);
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#endif
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