315 lines
14 KiB
C
315 lines
14 KiB
C
/*-
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********************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __AL_HAL_UNIT_ADAPTER_REGS_H__
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#define __AL_HAL_UNIT_ADAPTER_REGS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AL_PCI_COMMAND 0x04 /* 16 bits */
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#define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
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#define AL_PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define AL_PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define AL_PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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#define AL_PCI_BASE_ADDRESS_DEVICE_ID 0x0c
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#define AL_PCI_BASE_ADDRESS_0 0x10
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#define AL_PCI_BASE_ADDRESS_0_HI 0x14
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#define AL_PCI_BASE_ADDRESS_2 0x18
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#define AL_PCI_BASE_ADDRESS_2_HI 0x1c
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#define AL_PCI_BASE_ADDRESS_4 0x20
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#define AL_PCI_BASE_ADDRESS_4_HI 0x24
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#define AL_PCI_EXP_ROM_BASE_ADDRESS 0x30
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#define AL_PCI_AXI_CFG_AND_CTR_0 0x110
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#define AL_PCI_AXI_CFG_AND_CTR_1 0x130
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#define AL_PCI_AXI_CFG_AND_CTR_2 0x150
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#define AL_PCI_AXI_CFG_AND_CTR_3 0x170
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#define AL_PCI_APP_CONTROL 0x220
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#define AL_PCI_SRIOV_TOTAL_AND_INITIAL_VFS 0x30c
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#define AL_PCI_VF_BASE_ADDRESS_0 0x324
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#define AL_PCI_EXP_CAP_BASE 0x40
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#define AL_PCI_EXP_DEVCAP 4 /* Device capabilities */
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#define AL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
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#define AL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
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#define AL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
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#define AL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
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#define AL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
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#define AL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
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#define AL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
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#define AL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
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#define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
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#define AL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
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#define AL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
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#define AL_PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
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#define AL_PCI_EXP_DEVCTL 8 /* Device Control */
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#define AL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
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#define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
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#define AL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
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#define AL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
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#define AL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
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#define AL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
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#define AL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
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#define AL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
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#define AL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
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#define AL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
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#define AL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
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#define AL_PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
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#define AL_PCI_EXP_DEVSTA 0xA /* Device Status */
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#define AL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
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#define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
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#define AL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
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#define AL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
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#define AL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
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#define AL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
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#define AL_PCI_EXP_LNKCAP 0xC /* Link Capabilities */
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#define AL_PCI_EXP_LNKCAP_SLS 0xf /* Supported Link Speeds */
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#define AL_PCI_EXP_LNKCAP_SLS_2_5GB 0x1 /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
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#define AL_PCI_EXP_LNKCAP_SLS_5_0GB 0x2 /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
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#define AL_PCI_EXP_LNKCAP_MLW 0x3f0 /* Maximum Link Width */
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#define AL_PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
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#define AL_PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
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#define AL_PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
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#define AL_PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */
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#define AL_PCI_EXP_LNKCAP_SDERC 0x80000 /* Surprise Down Error Reporting Capable */
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#define AL_PCI_EXP_LNKCAP_DLLLARC 0x100000 /* Data Link Layer Link Active Reporting Capable */
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#define AL_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
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#define AL_PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
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#define AL_PCI_EXP_LNKCTL 0x10 /* Link Control */
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#define AL_PCI_EXP_LNKCTL_LNK_DIS 0x4 /* Link Disable Status */
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#define AL_PCI_EXP_LNKCTL_LNK_RTRN 0x5 /* Link Retrain Status */
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#define AL_PCI_EXP_LNKSTA 0x12 /* Link Status */
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#define AL_PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
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#define AL_PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
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#define AL_PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
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#define AL_PCI_EXP_LNKSTA_CLS_8_0GB 0x03 /* Current Link Speed 8.0GT/s */
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#define AL_PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
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#define AL_PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
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#define AL_PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
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#define AL_PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
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#define AL_PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
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#define AL_PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
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#define AL_PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
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#define AL_PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
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#define AL_PCI_MSIX_MSGCTRL 0 /* MSIX message control reg */
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#define AL_PCI_MSIX_MSGCTRL_TBL_SIZE 0x7ff /* MSIX table size */
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#define AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT 16 /* MSIX table size shift */
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#define AL_PCI_MSIX_MSGCTRL_EN 0x80000000 /* MSIX enable */
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#define AL_PCI_MSIX_MSGCTRL_MASK 0x40000000 /* MSIX mask */
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#define AL_PCI_MSIX_TABLE 0x4 /* MSIX table offset and bar reg */
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#define AL_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* MSIX table offset */
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#define AL_PCI_MSIX_TABLE_BAR 0x7 /* MSIX table BAR */
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#define AL_PCI_MSIX_PBA 0x8 /* MSIX pba offset and bar reg */
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#define AL_PCI_MSIX_PBA_OFFSET 0xfffffff8 /* MSIX pba offset */
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#define AL_PCI_MSIX_PBA_BAR 0x7 /* MSIX pba BAR */
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/* Adapter power management register 0 */
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#define AL_ADAPTER_PM_0 0x80
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#define AL_ADAPTER_PM_0_PM_NEXT_CAP_MASK 0xff00
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#define AL_ADAPTER_PM_0_PM_NEXT_CAP_SHIFT 8
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#define AL_ADAPTER_PM_0_PM_NEXT_CAP_VAL_MSIX 0x90
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/* Adapter power management register 1 */
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#define AL_ADAPTER_PM_1 0x84
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#define AL_ADAPTER_PM_1_PME_EN 0x100 /* PM enable */
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#define AL_ADAPTER_PM_1_PWR_STATE_MASK 0x3 /* PM state mask */
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#define AL_ADAPTER_PM_1_PWR_STATE_D3 0x3 /* PM D3 state */
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/* Sub Master Configuration & Control */
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#define AL_ADAPTER_SMCC 0x110
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#define AL_ADAPTER_SMCC_CONF_2 0x114
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/* Interrupt_Cause register */
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#define AL_ADAPTER_INT_CAUSE 0x1B0
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#define AL_ADAPTER_INT_CAUSE_WR_ERR AL_BIT(1)
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#define AL_ADAPTER_INT_CAUSE_RD_ERR AL_BIT(0)
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/* AXI_Master_Write_Error_Attribute_Latch register */
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/* AXI_Master_Read_Error_Attribute_Latch register */
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#define AL_ADAPTER_AXI_MSTR_WR_ERR_ATTR 0x1B4
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#define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR 0x1B8
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_MASK AL_FIELD_MASK(1, 0)
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_SHIFT 0
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_MASK AL_FIELD_MASK(4, 2)
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_SHIFT 2
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ADDR_TO AL_BIT(8)
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_ERR AL_BIT(9)
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_TO AL_BIT(10)
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#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ERR_BLK AL_BIT(11)
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#define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR_RD_PARITY_ERR AL_BIT(12)
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/* Interrupt_Cause_mask register */
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#define AL_ADAPTER_INT_CAUSE_MASK 0x1BC
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#define AL_ADAPTER_INT_CAUSE_MASK_WR_ERR AL_BIT(1)
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#define AL_ADAPTER_INT_CAUSE_MASK_RD_ERR AL_BIT(0)
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/* AXI_Master_write_error_address_Latch register */
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#define AL_ADAPTER_AXI_MSTR_WR_ERR_LO_LATCH 0x1C0
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/* AXI_Master_write_error_address_high_Latch register */
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#define AL_ADAPTER_AXI_MSTR_WR_ERR_HI_LATCH 0x1C4
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/* AXI_Master_read_error_address_Latch register */
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#define AL_ADAPTER_AXI_MSTR_RD_ERR_LO_LATCH 0x1C8
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/* AXI_Master_read_error_address_high_Latch register */
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#define AL_ADAPTER_AXI_MSTR_RD_ERR_HI_LATCH 0x1CC
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/* AXI_Master_Timeout register */
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#define AL_ADAPTER_AXI_MSTR_TO 0x1D0
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#define AL_ADAPTER_AXI_MSTR_TO_WR_MASK AL_FIELD_MASK(31, 16)
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#define AL_ADAPTER_AXI_MSTR_TO_WR_SHIFT 16
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#define AL_ADAPTER_AXI_MSTR_TO_RD_MASK AL_FIELD_MASK(15, 0)
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#define AL_ADAPTER_AXI_MSTR_TO_RD_SHIFT 0
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/*
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* Generic control registers
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*/
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/* Control 0 */
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#define AL_ADAPTER_GENERIC_CONTROL_0 0x1E0
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/* Control 2 */
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#define AL_ADAPTER_GENERIC_CONTROL_2 0x1E8
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/* Control 3 */
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#define AL_ADAPTER_GENERIC_CONTROL_3 0x1EC
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/* Control 9 */
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#define AL_ADAPTER_GENERIC_CONTROL_9 0x218
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/* Control 10 */
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#define AL_ADAPTER_GENERIC_CONTROL_10 0x21C
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/* Control 11 */
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#define AL_ADAPTER_GENERIC_CONTROL_11 0x220
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/* Control 12 */
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#define AL_ADAPTER_GENERIC_CONTROL_12 0x224
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/* Control 13 */
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#define AL_ADAPTER_GENERIC_CONTROL_13 0x228
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/* Control 14 */
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#define AL_ADAPTER_GENERIC_CONTROL_14 0x22C
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/* Control 15 */
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#define AL_ADAPTER_GENERIC_CONTROL_15 0x230
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/* Control 16 */
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#define AL_ADAPTER_GENERIC_CONTROL_16 0x234
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/* Control 17 */
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#define AL_ADAPTER_GENERIC_CONTROL_17 0x238
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/* Control 18 */
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#define AL_ADAPTER_GENERIC_CONTROL_18 0x23C
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/* Control 19 */
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#define AL_ADAPTER_GENERIC_CONTROL_19 0x240
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/* Enable clock gating */
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#define AL_ADAPTER_GENERIC_CONTROL_0_CLK_GATE_EN 0x01
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/* When set, all transactions through the PCI conf & mem BARs get timeout */
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#define AL_ADAPTER_GENERIC_CONTROL_0_ADAPTER_DIS 0x40
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#define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC AL_BIT(18)
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#define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC_ON_FLR AL_BIT(26)
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/*
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* SATA registers only
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*/
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/* Select 125MHz free running clock from IOFAB main PLL as SATA OOB clock
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* instead of using power management ref clock
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*/
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#define AL_ADAPTER_GENERIC_CONTROL_10_SATA_OOB_CLK_SEL AL_BIT(26)
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/* AXUSER selection and value per bit (1 = address, 0 = register) */
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/* Rx */
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#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_MASK AL_FIELD_MASK(15, 0)
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#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_SHIFT 0
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#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_MASK AL_FIELD_MASK(31, 16)
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#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_SHIFT 16
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/* Tx */
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#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_MASK AL_FIELD_MASK(15, 0)
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#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_SHIFT 0
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#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_MASK AL_FIELD_MASK(31, 16)
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#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_SHIFT 16
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/* Central Target-ID enabler. If set, then each entry will be used as programmed */
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#define AL_ADPTR_GEN_CTL_14_SATA_MSIX_TGTID_SEL AL_BIT(0)
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/* Allow access to store Target-ID values per entry */
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#define AL_ADPTR_GEN_CTL_14_SATA_MSIX_TGTID_ACCESS_EN AL_BIT(1)
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/* Target-ID Address select */
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/* Tx */
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#define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_MASK AL_FIELD_MASK(13, 8)
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#define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_SHIFT 8
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/* Rx */
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#define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_MASK AL_FIELD_MASK(21, 16)
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#define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_SHIFT 16
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/* Address Value */
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/* Rx */
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#define AL_ADPTR_GEN_CTL_15_SATA_VM_AWDDR_HI AL_FIELD_MASK(31, 0)
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/* Tx */
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#define AL_ADPTR_GEN_CTL_16_SATA_VM_ARDDR_HI AL_FIELD_MASK(31, 0)
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/*
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* ROB registers
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*/
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/* Read ROB Enable, when disabled the read ROB is bypassed */
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#define AL_ADPTR_GEN_CTL_19_READ_ROB_EN AL_BIT(0)
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/* Read force in-order of every read transaction */
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#define AL_ADPTR_GEN_CTL_19_READ_ROB_FORCE_INORDER AL_BIT(1)
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/* Read software reset */
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#define AL_ADPTR_GEN_CTL_19_READ_ROB_SW_RESET AL_BIT(15)
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/* Write ROB Enable, when disabled the Write ROB is bypassed */
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#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_EN AL_BIT(16)
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/* Write force in-order of every write transaction */
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#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_FORCE_INORDER AL_BIT(17)
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/* Write software reset */
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#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_SW_RESET AL_BIT(31)
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#ifdef __cplusplus
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}
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#endif
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#endif
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