e2ffdddc3a
The on-board NIC is an 3x3 AR9380 with 5GHz only. * enable pci code in AR9344_BASE * enable ath_pci and the firmware loading bits in DB120 * add in the relevant hints in DB120.hints to inform the probe/attach code where the PCIe fixup data is for the onboard chip. This is only relevant for a default development board. I also have a DB120 with the on-board PCIe wifi NIC disabled and it's exposed as a real PCIe slot (to put normal PCIe NICs in); the fixup code will need to be disabled to make this work correctly. Tested: * DB120
66 lines
1.6 KiB
Plaintext
66 lines
1.6 KiB
Plaintext
# This file (and the kernel config file accompanying it) are not designed
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# to be used by themselves. Instead, users of this file should create a
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# kernel # config file which includes this file (which gets the basic hints),
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# then override the default options (adding devices as needed) and adding
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# hints as needed (for example, the GPIO and LAN PHY.)
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# $FreeBSD$
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hint.apb.0.at="nexus0"
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hint.apb.0.irq=4
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# uart0
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hint.uart.0.at="apb0"
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# NB: This isn't an ns8250 UART
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hint.uart.0.maddr=0x18020003
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hint.uart.0.msize=0x18
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hint.uart.0.irq=3
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#ehci - note the 0x100 offset for the AR913x/AR724x
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hint.ehci.0.at="nexus0"
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hint.ehci.0.maddr=0x1b000100
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hint.ehci.0.msize=0x00001000
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hint.ehci.0.irq=1
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# pci
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hint.pcib.0.at="nexus0"
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hint.pcib.0.irq=0
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hint.arge.0.at="nexus0"
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hint.arge.0.maddr=0x19000000
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hint.arge.0.msize=0x1000
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hint.arge.0.irq=2
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hint.arge.1.at="nexus0"
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hint.arge.1.maddr=0x1a000000
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hint.arge.1.msize=0x1000
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hint.arge.1.irq=3
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# XXX The ath device hangs off of the AHB, rather than the Nexus.
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hint.ath.0.at="nexus0"
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hint.ath.0.maddr=0x18100000
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hint.ath.0.msize=0x20000
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hint.ath.0.irq=0
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hint.ath.0.vendor_id=0x168c
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hint.ath.0.device_id=0x0031
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# Set this to define where the ath calibration data
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# should be fetched from in physical memory.
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# hint.ath.0.eepromaddr=0x1fff1000
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# SPI flash
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hint.spi.0.at="nexus0"
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hint.spi.0.maddr=0x1f000000
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hint.spi.0.msize=0x10
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hint.mx25l.0.at="spibus0"
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hint.mx25l.0.cs=0
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# Watchdog
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hint.ar71xx_wdog.0.at="nexus0"
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# The GPIO function and pin mask is configured per-board
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hint.gpio.0.at="apb0"
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hint.gpio.0.maddr=0x18040000
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hint.gpio.0.msize=0x1000
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hint.gpio.0.irq=2
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