785acb1fd1
MFC after: 2 weeks
526 lines
14 KiB
C
526 lines
14 KiB
C
/*-
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* Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
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* southbridges.
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* Please see the following specifications for the descriptions of the
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* registers and flags:
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* - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf
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* - AMD SB700/710/750 Register Reference Guide (RRG)
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* http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf
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* - AMD SB700/710/750 Register Programming Requirements (RPR)
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* http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf
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* - AMD SB800-Series Southbridges Register Reference Guide (RRG)
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* http://support.amd.com/us/Embedded_TechDocs/45482.pdf
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* Please see the following for Watchdog Resource Table specification:
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* - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
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* http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx
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* AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above
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* specifications, but the table hasn't been spotted in the wild yet.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/sysctl.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <sys/watchdog.h>
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#include <dev/pci/pcivar.h>
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#include <isa/isavar.h>
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/* SB7xx RRG 2.3.3.1.1. */
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#define AMDSB_PMIO_INDEX 0xcd6
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#define AMDSB_PMIO_DATA (PMIO_INDEX + 1)
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#define AMDSB_PMIO_WIDTH 2
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/* SB7xx RRG 2.3.3.2. */
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#define AMDSB_PM_RESET_STATUS0 0x44
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#define AMDSB_PM_RESET_STATUS1 0x45
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#define AMDSB_WD_RST_STS 0x02
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/* SB7xx RRG 2.3.3.2, RPR 2.36. */
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#define AMDSB_PM_WDT_CTRL 0x69
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#define AMDSB_WDT_DISABLE 0x01
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#define AMDSB_WDT_RES_MASK (0x02 | 0x04)
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#define AMDSB_WDT_RES_32US 0x00
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#define AMDSB_WDT_RES_10MS 0x02
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#define AMDSB_WDT_RES_100MS 0x04
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#define AMDSB_WDT_RES_1S 0x06
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#define AMDSB_PM_WDT_BASE_LSB 0x6c
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#define AMDSB_PM_WDT_BASE_MSB 0x6f
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/* SB8xx RRG 2.3.3. */
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#define AMDSB8_PM_WDT_EN 0x48
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#define AMDSB8_WDT_DEC_EN 0x01
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#define AMDSB8_WDT_DISABLE 0x02
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#define AMDSB8_PM_WDT_CTRL 0x4c
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#define AMDSB8_WDT_32KHZ 0x00
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#define AMDSB8_WDT_1HZ 0x03
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#define AMDSB8_WDT_RES_MASK 0x03
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#define AMDSB8_PM_RESET_STATUS0 0xC0
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#define AMDSB8_PM_RESET_STATUS1 0xC1
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#define AMDSB8_WD_RST_STS 0x20
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/* SB7xx RRG 2.3.4, WDRT. */
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#define AMDSB_WD_CTRL 0x00
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#define AMDSB_WD_RUN 0x01
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#define AMDSB_WD_FIRED 0x02
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#define AMDSB_WD_SHUTDOWN 0x04
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#define AMDSB_WD_DISABLE 0x08
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#define AMDSB_WD_RESERVED 0x70
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#define AMDSB_WD_RELOAD 0x80
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#define AMDSB_WD_COUNT 0x04
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#define AMDSB_WD_COUNT_MASK 0xffff
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#define AMDSB_WDIO_REG_WIDTH 4
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/* WDRT */
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#define MAXCOUNT_MIN_VALUE 511
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/* SB7xx RRG 2.3.1.1, SB600 RRG 2.3.1.1, SB8xx RRG 2.3.1. */
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#define AMDSB_SMBUS_DEVID 0x43851002
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#define AMDSB8_SMBUS_REVID 0x40
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#define AMDHUDSON_SMBUS_DEVID 0x780b1022
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#define AMDKERNCZ_SMBUS_DEVID 0x790b1022
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#define amdsbwd_verbose_printf(dev, ...) \
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do { \
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if (bootverbose) \
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device_printf(dev, __VA_ARGS__);\
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} while (0)
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struct amdsbwd_softc {
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device_t dev;
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eventhandler_tag ev_tag;
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struct resource *res_ctrl;
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struct resource *res_count;
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int rid_ctrl;
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int rid_count;
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int ms_per_tick;
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int max_ticks;
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int active;
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unsigned int timeout;
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};
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static void amdsbwd_identify(driver_t *driver, device_t parent);
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static int amdsbwd_probe(device_t dev);
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static int amdsbwd_attach(device_t dev);
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static int amdsbwd_detach(device_t dev);
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static device_method_t amdsbwd_methods[] = {
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DEVMETHOD(device_identify, amdsbwd_identify),
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DEVMETHOD(device_probe, amdsbwd_probe),
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DEVMETHOD(device_attach, amdsbwd_attach),
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DEVMETHOD(device_detach, amdsbwd_detach),
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#if 0
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DEVMETHOD(device_shutdown, amdsbwd_detach),
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#endif
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DEVMETHOD_END
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};
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static devclass_t amdsbwd_devclass;
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static driver_t amdsbwd_driver = {
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"amdsbwd",
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amdsbwd_methods,
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sizeof(struct amdsbwd_softc)
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};
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DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL);
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static uint8_t
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pmio_read(struct resource *res, uint8_t reg)
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{
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bus_write_1(res, 0, reg); /* Index */
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return (bus_read_1(res, 1)); /* Data */
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}
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static void
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pmio_write(struct resource *res, uint8_t reg, uint8_t val)
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{
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bus_write_1(res, 0, reg); /* Index */
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bus_write_1(res, 1, val); /* Data */
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}
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static uint32_t
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wdctrl_read(struct amdsbwd_softc *sc)
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{
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return (bus_read_4(sc->res_ctrl, 0));
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}
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static void
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wdctrl_write(struct amdsbwd_softc *sc, uint32_t val)
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{
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bus_write_4(sc->res_ctrl, 0, val);
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}
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static __unused uint32_t
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wdcount_read(struct amdsbwd_softc *sc)
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{
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return (bus_read_4(sc->res_count, 0));
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}
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static void
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wdcount_write(struct amdsbwd_softc *sc, uint32_t val)
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{
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bus_write_4(sc->res_count, 0, val);
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}
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static void
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amdsbwd_tmr_enable(struct amdsbwd_softc *sc)
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{
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uint32_t val;
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val = wdctrl_read(sc);
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val |= AMDSB_WD_RUN;
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wdctrl_write(sc, val);
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sc->active = 1;
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amdsbwd_verbose_printf(sc->dev, "timer enabled\n");
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}
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static void
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amdsbwd_tmr_disable(struct amdsbwd_softc *sc)
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{
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uint32_t val;
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val = wdctrl_read(sc);
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val &= ~AMDSB_WD_RUN;
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wdctrl_write(sc, val);
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sc->active = 0;
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amdsbwd_verbose_printf(sc->dev, "timer disabled\n");
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}
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static void
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amdsbwd_tmr_reload(struct amdsbwd_softc *sc)
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{
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uint32_t val;
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val = wdctrl_read(sc);
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val |= AMDSB_WD_RELOAD;
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wdctrl_write(sc, val);
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}
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static void
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amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout)
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{
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timeout &= AMDSB_WD_COUNT_MASK;
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wdcount_write(sc, timeout);
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sc->timeout = timeout;
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amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout);
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}
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static void
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amdsbwd_event(void *arg, unsigned int cmd, int *error)
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{
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struct amdsbwd_softc *sc = arg;
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unsigned int timeout;
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/* convert from power-of-two-ns to WDT ticks */
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cmd &= WD_INTERVAL;
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if (cmd < WD_TO_1SEC)
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cmd = 0;
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if (cmd) {
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timeout = ((uint64_t)1 << (cmd - WD_TO_1MS)) / sc->ms_per_tick;
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if (timeout > sc->max_ticks)
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timeout = sc->max_ticks;
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if (timeout != sc->timeout) {
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amdsbwd_tmr_set(sc, timeout);
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if (!sc->active)
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amdsbwd_tmr_enable(sc);
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}
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amdsbwd_tmr_reload(sc);
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*error = 0;
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} else {
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if (sc->active)
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amdsbwd_tmr_disable(sc);
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}
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}
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static void
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amdsbwd_identify(driver_t *driver, device_t parent)
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{
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device_t child;
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device_t smb_dev;
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if (resource_disabled("amdsbwd", 0))
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return;
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if (device_find_child(parent, "amdsbwd", -1) != NULL)
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return;
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/*
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* Try to identify SB600/SB7xx by PCI Device ID of SMBus device
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* that should be present at bus 0, device 20, function 0.
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*/
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smb_dev = pci_find_bsf(0, 20, 0);
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if (smb_dev == NULL)
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return;
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if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID &&
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pci_get_devid(smb_dev) != AMDHUDSON_SMBUS_DEVID &&
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pci_get_devid(smb_dev) != AMDKERNCZ_SMBUS_DEVID)
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return;
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child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1);
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if (child == NULL)
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device_printf(parent, "add amdsbwd child failed\n");
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}
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static void
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amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr)
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{
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uint32_t val;
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int i;
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/* Report cause of previous reset for user's convenience. */
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val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0);
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if (val != 0)
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amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
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val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1);
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if (val != 0)
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amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
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if ((val & AMDSB_WD_RST_STS) != 0)
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device_printf(dev, "Previous Reset was caused by Watchdog\n");
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/* Find base address of memory mapped WDT registers. */
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for (*addr = 0, i = 0; i < 4; i++) {
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*addr <<= 8;
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*addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i);
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}
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*addr &= ~0x07u;
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/* Set watchdog timer tick to 1s. */
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val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
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val &= ~AMDSB_WDT_RES_MASK;
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val |= AMDSB_WDT_RES_1S;
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pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
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/* Enable watchdog device (in stopped state). */
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val = pmio_read(pmres, AMDSB_PM_WDT_CTRL);
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val &= ~AMDSB_WDT_DISABLE;
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pmio_write(pmres, AMDSB_PM_WDT_CTRL, val);
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/*
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* XXX TODO: Ensure that watchdog decode is enabled
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* (register 0x41, bit 3).
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*/
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device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer");
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}
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static void
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amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr)
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{
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uint32_t val;
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int i;
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/* Report cause of previous reset for user's convenience. */
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val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0);
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if (val != 0)
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amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val);
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val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1);
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if (val != 0)
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amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val);
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if ((val & AMDSB8_WD_RST_STS) != 0)
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device_printf(dev, "Previous Reset was caused by Watchdog\n");
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/* Find base address of memory mapped WDT registers. */
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for (*addr = 0, i = 0; i < 4; i++) {
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*addr <<= 8;
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*addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i);
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}
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*addr &= ~0x07u;
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/* Set watchdog timer tick to 1s. */
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val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
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val &= ~AMDSB8_WDT_RES_MASK;
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val |= AMDSB8_WDT_1HZ;
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pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val);
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#ifdef AMDSBWD_DEBUG
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val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL);
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amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#02x\n", val);
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#endif
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/*
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* Enable watchdog device (in stopped state)
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* and decoding of its address.
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*/
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val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
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val &= ~AMDSB8_WDT_DISABLE;
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val |= AMDSB8_WDT_DEC_EN;
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pmio_write(pmres, AMDSB8_PM_WDT_EN, val);
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#ifdef AMDSBWD_DEBUG
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val = pmio_read(pmres, AMDSB8_PM_WDT_EN);
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device_printf(dev, "AMDSB8_PM_WDT_EN value = %#02x\n", val);
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#endif
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device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer");
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}
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static int
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amdsbwd_probe(device_t dev)
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{
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struct resource *res;
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device_t smb_dev;
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uint32_t addr;
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int rid;
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int rc;
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/* Do not claim some ISA PnP device by accident. */
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if (isa_get_logicalid(dev) != 0)
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return (ENXIO);
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rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX,
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AMDSB_PMIO_WIDTH);
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for IO failed\n");
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return (ENXIO);
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}
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rid = 0;
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res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (res == NULL) {
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device_printf(dev, "bus_alloc_resource for IO failed\n");
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return (ENXIO);
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}
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smb_dev = pci_find_bsf(0, 20, 0);
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KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
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if (pci_get_devid(smb_dev) == AMDSB_SMBUS_DEVID &&
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pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID)
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amdsbwd_probe_sb7xx(dev, res, &addr);
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else
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amdsbwd_probe_sb8xx(dev, res, &addr);
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bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
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bus_delete_resource(dev, SYS_RES_IOPORT, rid);
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amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr);
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rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL,
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AMDSB_WDIO_REG_WIDTH);
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for control failed\n");
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return (ENXIO);
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}
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rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT,
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AMDSB_WDIO_REG_WIDTH);
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if (rc != 0) {
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device_printf(dev, "bus_set_resource for count failed\n");
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return (ENXIO);
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}
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return (0);
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}
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static int
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amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc)
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{
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device_t smb_dev;
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sc->max_ticks = UINT16_MAX;
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sc->rid_ctrl = 0;
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sc->rid_count = 1;
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smb_dev = pci_find_bsf(0, 20, 0);
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KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n"));
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sc->ms_per_tick = 1000;
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sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&sc->rid_ctrl, RF_ACTIVE);
|
|
if (sc->res_ctrl == NULL) {
|
|
device_printf(dev, "bus_alloc_resource for ctrl failed\n");
|
|
return (ENXIO);
|
|
}
|
|
sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&sc->rid_count, RF_ACTIVE);
|
|
if (sc->res_count == NULL) {
|
|
device_printf(dev, "bus_alloc_resource for count failed\n");
|
|
return (ENXIO);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
amdsbwd_attach(device_t dev)
|
|
{
|
|
struct amdsbwd_softc *sc;
|
|
int rc;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
rc = amdsbwd_attach_sb(dev, sc);
|
|
if (rc != 0)
|
|
goto fail;
|
|
|
|
#ifdef AMDSBWD_DEBUG
|
|
device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc));
|
|
device_printf(dev, "wd count = %#04x\n", wdcount_read(sc));
|
|
#endif
|
|
|
|
/* Setup initial state of Watchdog Control. */
|
|
wdctrl_write(sc, AMDSB_WD_FIRED);
|
|
|
|
if (wdctrl_read(sc) & AMDSB_WD_DISABLE) {
|
|
device_printf(dev, "watchdog hardware is disabled\n");
|
|
goto fail;
|
|
}
|
|
|
|
sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc,
|
|
EVENTHANDLER_PRI_ANY);
|
|
|
|
return (0);
|
|
|
|
fail:
|
|
amdsbwd_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
amdsbwd_detach(device_t dev)
|
|
{
|
|
struct amdsbwd_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (sc->ev_tag != NULL)
|
|
EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
|
|
|
|
if (sc->active)
|
|
amdsbwd_tmr_disable(sc);
|
|
|
|
if (sc->res_ctrl != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl,
|
|
sc->res_ctrl);
|
|
|
|
if (sc->res_count != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count,
|
|
sc->res_count);
|
|
|
|
return (0);
|
|
}
|
|
|