e439783711
coalescing and zipping multiple CQEs into a single merged CQE. The feature is enabled by default and can be disabled by a sysctl. Implementing this feature mlx5_cqwq_pop() has been separated from mlx5e_get_cqe(). MFC after: 1 week Submitted by: Mark Bloch <markb@mellanox.com> Differential Revision: https://reviews.freebsd.org/D4598 Sponsored by: Mellanox Technologies
1256 lines
28 KiB
C
1256 lines
28 KiB
C
/*-
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* Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef MLX5_DEVICE_H
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#define MLX5_DEVICE_H
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#include <linux/types.h>
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#include <rdma/ib_verbs.h>
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#include <dev/mlx5/mlx5_ifc.h>
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#define FW_INIT_TIMEOUT_MILI 2000
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#define FW_INIT_WAIT_MS 2
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#if defined(__LITTLE_ENDIAN)
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#define MLX5_SET_HOST_ENDIANNESS 0
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#elif defined(__BIG_ENDIAN)
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#define MLX5_SET_HOST_ENDIANNESS 0x80
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#else
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#error Host endianness not defined
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#endif
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/* helper macros */
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#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
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#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
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#define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
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#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
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#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
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#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
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#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
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#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
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#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
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#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
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#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
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#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
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#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
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#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
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#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
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#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
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/* insert a value to a struct */
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#define MLX5_SET(typ, p, fld, v) do { \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
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BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
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*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_SET_TO_ONES(typ, p, fld) do { \
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BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
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BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
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*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
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cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
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(~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
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<< __mlx5_dw_bit_off(typ, fld))); \
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} while (0)
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#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
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__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
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__mlx5_mask(typ, fld))
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#define MLX5_GET_PR(typ, p, fld) ({ \
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u32 ___t = MLX5_GET(typ, p, fld); \
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pr_debug(#fld " = 0x%x\n", ___t); \
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___t; \
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})
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#define MLX5_SET64(typ, p, fld, v) do { \
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BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
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BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
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*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
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} while (0)
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#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
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enum {
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MLX5_MAX_COMMANDS = 32,
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MLX5_CMD_DATA_BLOCK_SIZE = 512,
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MLX5_PCI_CMD_XPORT = 7,
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MLX5_MKEY_BSF_OCTO_SIZE = 4,
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MLX5_MAX_PSVS = 4,
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};
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enum {
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MLX5_EXTENDED_UD_AV = 0x80000000,
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};
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enum {
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MLX5_STAT_RATE_OFFSET = 5,
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};
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enum {
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MLX5_INLINE_SEG = 0x80000000,
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};
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enum {
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MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
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};
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enum {
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MLX5_MIN_PKEY_TABLE_SIZE = 128,
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MLX5_MAX_LOG_PKEY_TABLE = 5,
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};
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enum {
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MLX5_PERM_LOCAL_READ = 1 << 2,
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MLX5_PERM_LOCAL_WRITE = 1 << 3,
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MLX5_PERM_REMOTE_READ = 1 << 4,
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MLX5_PERM_REMOTE_WRITE = 1 << 5,
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MLX5_PERM_ATOMIC = 1 << 6,
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MLX5_PERM_UMR_EN = 1 << 7,
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};
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enum {
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MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
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MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
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MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
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MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
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MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
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};
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enum {
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MLX5_MKEY_REMOTE_INVAL = 1 << 24,
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MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
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MLX5_MKEY_BSF_EN = 1 << 30,
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MLX5_MKEY_LEN64 = 1 << 31,
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};
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enum {
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MLX5_EN_RD = (u64)1,
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MLX5_EN_WR = (u64)2
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};
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enum {
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MLX5_BF_REGS_PER_PAGE = 4,
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MLX5_MAX_UAR_PAGES = 1 << 8,
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MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
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MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
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};
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enum {
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MLX5_MKEY_MASK_LEN = 1ull << 0,
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MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
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MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
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MLX5_MKEY_MASK_PD = 1ull << 7,
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MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
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MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
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MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
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MLX5_MKEY_MASK_KEY = 1ull << 13,
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MLX5_MKEY_MASK_QPN = 1ull << 14,
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MLX5_MKEY_MASK_LR = 1ull << 17,
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MLX5_MKEY_MASK_LW = 1ull << 18,
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MLX5_MKEY_MASK_RR = 1ull << 19,
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MLX5_MKEY_MASK_RW = 1ull << 20,
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MLX5_MKEY_MASK_A = 1ull << 21,
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MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
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MLX5_MKEY_MASK_FREE = 1ull << 29,
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};
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enum {
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MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
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MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
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MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
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MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
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MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
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MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
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MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
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};
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enum {
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MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
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MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
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MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
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MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
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MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
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MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
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MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
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MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
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MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
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MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
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MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
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MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
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MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
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};
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enum {
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MLX5_ROCE_VERSION_1 = 0,
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MLX5_ROCE_VERSION_1_5 = 1,
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MLX5_ROCE_VERSION_2 = 2,
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};
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enum {
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MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
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MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
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MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
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};
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enum {
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MLX5_ROCE_L3_TYPE_IPV4 = 0,
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MLX5_ROCE_L3_TYPE_IPV6 = 1,
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};
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enum {
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MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
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MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
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};
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enum {
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MLX5_OPCODE_NOP = 0x00,
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MLX5_OPCODE_SEND_INVAL = 0x01,
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MLX5_OPCODE_RDMA_WRITE = 0x08,
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MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
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MLX5_OPCODE_SEND = 0x0a,
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MLX5_OPCODE_SEND_IMM = 0x0b,
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MLX5_OPCODE_LSO = 0x0e,
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MLX5_OPCODE_RDMA_READ = 0x10,
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MLX5_OPCODE_ATOMIC_CS = 0x11,
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MLX5_OPCODE_ATOMIC_FA = 0x12,
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MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
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MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
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MLX5_OPCODE_BIND_MW = 0x18,
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MLX5_OPCODE_CONFIG_CMD = 0x1f,
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MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
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MLX5_RECV_OPCODE_SEND = 0x01,
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MLX5_RECV_OPCODE_SEND_IMM = 0x02,
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MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
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MLX5_CQE_OPCODE_ERROR = 0x1e,
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MLX5_CQE_OPCODE_RESIZE = 0x16,
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MLX5_OPCODE_SET_PSV = 0x20,
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MLX5_OPCODE_GET_PSV = 0x21,
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MLX5_OPCODE_CHECK_PSV = 0x22,
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MLX5_OPCODE_RGET_PSV = 0x26,
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MLX5_OPCODE_RCHECK_PSV = 0x27,
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MLX5_OPCODE_UMR = 0x25,
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};
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enum {
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MLX5_SET_PORT_RESET_QKEY = 0,
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MLX5_SET_PORT_GUID0 = 16,
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MLX5_SET_PORT_NODE_GUID = 17,
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MLX5_SET_PORT_SYS_GUID = 18,
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MLX5_SET_PORT_GID_TABLE = 19,
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MLX5_SET_PORT_PKEY_TABLE = 20,
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};
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enum {
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MLX5_MAX_PAGE_SHIFT = 31
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};
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enum {
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MLX5_ADAPTER_PAGE_SHIFT = 12,
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MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
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};
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enum {
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MLX5_CAP_OFF_CMDIF_CSUM = 46,
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};
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struct mlx5_inbox_hdr {
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__be16 opcode;
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u8 rsvd[4];
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__be16 opmod;
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};
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struct mlx5_outbox_hdr {
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u8 status;
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u8 rsvd[3];
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__be32 syndrome;
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};
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struct mlx5_cmd_layout {
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u8 type;
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u8 rsvd0[3];
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__be32 inlen;
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__be64 in_ptr;
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__be32 in[4];
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__be32 out[4];
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__be64 out_ptr;
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__be32 outlen;
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u8 token;
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u8 sig;
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u8 rsvd1;
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u8 status_own;
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};
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struct mlx5_health_buffer {
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__be32 assert_var[5];
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__be32 rsvd0[3];
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__be32 assert_exit_ptr;
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__be32 assert_callra;
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__be32 rsvd1[2];
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__be32 fw_ver;
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__be32 hw_id;
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__be32 rsvd2;
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u8 irisc_index;
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u8 synd;
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__be16 ext_sync;
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};
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struct mlx5_init_seg {
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__be32 fw_rev;
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__be32 cmdif_rev_fw_sub;
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__be32 rsvd0[2];
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__be32 cmdq_addr_h;
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__be32 cmdq_addr_l_sz;
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__be32 cmd_dbell;
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__be32 rsvd1[120];
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__be32 initializing;
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struct mlx5_health_buffer health;
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__be32 rsvd2[884];
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__be32 health_counter;
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__be32 rsvd3[1019];
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__be64 ieee1588_clk;
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__be32 ieee1588_clk_type;
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__be32 clr_intx;
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};
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struct mlx5_eqe_comp {
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__be32 reserved[6];
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__be32 cqn;
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};
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struct mlx5_eqe_qp_srq {
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__be32 reserved[6];
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__be32 qp_srq_n;
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};
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struct mlx5_eqe_cq_err {
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__be32 cqn;
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u8 reserved1[7];
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u8 syndrome;
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};
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struct mlx5_eqe_port_state {
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u8 reserved0[8];
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u8 port;
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};
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struct mlx5_eqe_gpio {
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__be32 reserved0[2];
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__be64 gpio_event;
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};
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struct mlx5_eqe_congestion {
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u8 type;
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u8 rsvd0;
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u8 congestion_level;
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};
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struct mlx5_eqe_stall_vl {
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u8 rsvd0[3];
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u8 port_vl;
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};
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struct mlx5_eqe_cmd {
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__be32 vector;
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__be32 rsvd[6];
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};
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struct mlx5_eqe_page_req {
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u8 rsvd0[2];
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__be16 func_id;
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__be32 num_pages;
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__be32 rsvd1[5];
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};
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struct mlx5_eqe_vport_change {
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u8 rsvd0[2];
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__be16 vport_num;
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__be32 rsvd1[6];
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};
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#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
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#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
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enum {
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MLX5_MODULE_STATUS_PLUGGED = 0x1,
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MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
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MLX5_MODULE_STATUS_ERROR = 0x3,
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};
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enum {
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MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
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MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
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MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
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MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
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MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
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MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 0x5,
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MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
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};
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struct mlx5_eqe_port_module_event {
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u8 rsvd0;
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u8 module;
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u8 rsvd1;
|
|
u8 module_status;
|
|
u8 rsvd2[2];
|
|
u8 error_type;
|
|
};
|
|
|
|
union ev_data {
|
|
__be32 raw[7];
|
|
struct mlx5_eqe_cmd cmd;
|
|
struct mlx5_eqe_comp comp;
|
|
struct mlx5_eqe_qp_srq qp_srq;
|
|
struct mlx5_eqe_cq_err cq_err;
|
|
struct mlx5_eqe_port_state port;
|
|
struct mlx5_eqe_gpio gpio;
|
|
struct mlx5_eqe_congestion cong;
|
|
struct mlx5_eqe_stall_vl stall_vl;
|
|
struct mlx5_eqe_page_req req_pages;
|
|
struct mlx5_eqe_port_module_event port_module_event;
|
|
struct mlx5_eqe_vport_change vport_change;
|
|
} __packed;
|
|
|
|
struct mlx5_eqe {
|
|
u8 rsvd0;
|
|
u8 type;
|
|
u8 rsvd1;
|
|
u8 sub_type;
|
|
__be32 rsvd2[7];
|
|
union ev_data data;
|
|
__be16 rsvd3;
|
|
u8 signature;
|
|
u8 owner;
|
|
} __packed;
|
|
|
|
struct mlx5_cmd_prot_block {
|
|
u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
|
|
u8 rsvd0[48];
|
|
__be64 next;
|
|
__be32 block_num;
|
|
u8 rsvd1;
|
|
u8 token;
|
|
u8 ctrl_sig;
|
|
u8 sig;
|
|
};
|
|
|
|
enum {
|
|
MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
|
|
};
|
|
|
|
struct mlx5_err_cqe {
|
|
u8 rsvd0[32];
|
|
__be32 srqn;
|
|
u8 rsvd1[18];
|
|
u8 vendor_err_synd;
|
|
u8 syndrome;
|
|
__be32 s_wqe_opcode_qpn;
|
|
__be16 wqe_counter;
|
|
u8 signature;
|
|
u8 op_own;
|
|
};
|
|
|
|
struct mlx5_cqe64 {
|
|
u8 tunneled_etc;
|
|
u8 rsvd0[3];
|
|
u8 lro_tcppsh_abort_dupack;
|
|
u8 lro_min_ttl;
|
|
__be16 lro_tcp_win;
|
|
__be32 lro_ack_seq_num;
|
|
__be32 rss_hash_result;
|
|
u8 rss_hash_type;
|
|
u8 ml_path;
|
|
u8 rsvd20[2];
|
|
__be16 check_sum;
|
|
__be16 slid;
|
|
__be32 flags_rqpn;
|
|
u8 hds_ip_ext;
|
|
u8 l4_hdr_type_etc;
|
|
__be16 vlan_info;
|
|
__be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
|
|
__be32 imm_inval_pkey;
|
|
u8 rsvd40[4];
|
|
__be32 byte_cnt;
|
|
__be64 timestamp;
|
|
__be32 sop_drop_qpn;
|
|
__be16 wqe_counter;
|
|
u8 signature;
|
|
u8 op_own;
|
|
};
|
|
|
|
static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
|
|
}
|
|
|
|
static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
|
|
}
|
|
|
|
static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->l4_hdr_type_etc >> 4) & 0x7;
|
|
}
|
|
|
|
static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return be16_to_cpu(cqe->vlan_info) & 0xfff;
|
|
}
|
|
|
|
static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
|
|
{
|
|
memcpy(smac, &cqe->rss_hash_type , 4);
|
|
memcpy(smac + 4, &cqe->slid , 2);
|
|
}
|
|
|
|
static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return cqe->l4_hdr_type_etc & 0x1;
|
|
}
|
|
|
|
static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
|
|
{
|
|
return cqe->tunneled_etc & 0x1;
|
|
}
|
|
|
|
enum {
|
|
CQE_L4_HDR_TYPE_NONE = 0x0,
|
|
CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
|
|
CQE_L4_HDR_TYPE_UDP = 0x2,
|
|
CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
|
|
CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
|
|
};
|
|
|
|
enum {
|
|
/* source L3 hash types */
|
|
CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
|
|
CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
|
|
CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
|
|
|
|
/* destination L3 hash types */
|
|
CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
|
|
CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
|
|
CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
|
|
|
|
/* source L4 hash types */
|
|
CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
|
|
CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
|
|
CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
|
|
CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
|
|
|
|
/* destination L4 hash types */
|
|
CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
|
|
CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
|
|
CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
|
|
CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
|
|
};
|
|
|
|
enum {
|
|
CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
|
|
CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
|
|
CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
|
|
};
|
|
|
|
enum {
|
|
CQE_L2_OK = 1 << 0,
|
|
CQE_L3_OK = 1 << 1,
|
|
CQE_L4_OK = 1 << 2,
|
|
};
|
|
|
|
struct mlx5_sig_err_cqe {
|
|
u8 rsvd0[16];
|
|
__be32 expected_trans_sig;
|
|
__be32 actual_trans_sig;
|
|
__be32 expected_reftag;
|
|
__be32 actual_reftag;
|
|
__be16 syndrome;
|
|
u8 rsvd22[2];
|
|
__be32 mkey;
|
|
__be64 err_offset;
|
|
u8 rsvd30[8];
|
|
__be32 qpn;
|
|
u8 rsvd38[2];
|
|
u8 signature;
|
|
u8 op_own;
|
|
};
|
|
|
|
struct mlx5_wqe_srq_next_seg {
|
|
u8 rsvd0[2];
|
|
__be16 next_wqe_index;
|
|
u8 signature;
|
|
u8 rsvd1[11];
|
|
};
|
|
|
|
union mlx5_ext_cqe {
|
|
struct ib_grh grh;
|
|
u8 inl[64];
|
|
};
|
|
|
|
struct mlx5_cqe128 {
|
|
union mlx5_ext_cqe inl_grh;
|
|
struct mlx5_cqe64 cqe64;
|
|
};
|
|
|
|
struct mlx5_srq_ctx {
|
|
u8 state_log_sz;
|
|
u8 rsvd0[3];
|
|
__be32 flags_xrcd;
|
|
__be32 pgoff_cqn;
|
|
u8 rsvd1[4];
|
|
u8 log_pg_sz;
|
|
u8 rsvd2[7];
|
|
__be32 pd;
|
|
__be16 lwm;
|
|
__be16 wqe_cnt;
|
|
u8 rsvd3[8];
|
|
__be64 db_record;
|
|
};
|
|
|
|
struct mlx5_create_srq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 input_srqn;
|
|
u8 rsvd0[4];
|
|
struct mlx5_srq_ctx ctx;
|
|
u8 rsvd1[208];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_create_srq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
__be32 srqn;
|
|
u8 rsvd[4];
|
|
};
|
|
|
|
struct mlx5_destroy_srq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 srqn;
|
|
u8 rsvd[4];
|
|
};
|
|
|
|
struct mlx5_destroy_srq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
struct mlx5_query_srq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 srqn;
|
|
u8 rsvd0[4];
|
|
};
|
|
|
|
struct mlx5_query_srq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd0[8];
|
|
struct mlx5_srq_ctx ctx;
|
|
u8 rsvd1[32];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_arm_srq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 srqn;
|
|
__be16 rsvd;
|
|
__be16 lwm;
|
|
};
|
|
|
|
struct mlx5_arm_srq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
struct mlx5_cq_context {
|
|
u8 status;
|
|
u8 cqe_sz_flags;
|
|
u8 st;
|
|
u8 rsvd3;
|
|
u8 rsvd4[6];
|
|
__be16 page_offset;
|
|
__be32 log_sz_usr_page;
|
|
__be16 cq_period;
|
|
__be16 cq_max_count;
|
|
__be16 rsvd20;
|
|
__be16 c_eqn;
|
|
u8 log_pg_sz;
|
|
u8 rsvd25[7];
|
|
__be32 last_notified_index;
|
|
__be32 solicit_producer_index;
|
|
__be32 consumer_counter;
|
|
__be32 producer_counter;
|
|
u8 rsvd48[8];
|
|
__be64 db_record_addr;
|
|
};
|
|
|
|
struct mlx5_create_cq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 input_cqn;
|
|
u8 rsvdx[4];
|
|
struct mlx5_cq_context ctx;
|
|
u8 rsvd6[192];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_create_cq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
__be32 cqn;
|
|
u8 rsvd0[4];
|
|
};
|
|
|
|
struct mlx5_destroy_cq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 cqn;
|
|
u8 rsvd0[4];
|
|
};
|
|
|
|
struct mlx5_destroy_cq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd0[8];
|
|
};
|
|
|
|
struct mlx5_query_cq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 cqn;
|
|
u8 rsvd0[4];
|
|
};
|
|
|
|
struct mlx5_query_cq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd0[8];
|
|
struct mlx5_cq_context ctx;
|
|
u8 rsvd6[16];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_modify_cq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 cqn;
|
|
__be32 field_select;
|
|
struct mlx5_cq_context ctx;
|
|
u8 rsvd[192];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_modify_cq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
struct mlx5_eq_context {
|
|
u8 status;
|
|
u8 ec_oi;
|
|
u8 st;
|
|
u8 rsvd2[7];
|
|
__be16 page_pffset;
|
|
__be32 log_sz_usr_page;
|
|
u8 rsvd3[7];
|
|
u8 intr;
|
|
u8 log_page_size;
|
|
u8 rsvd4[15];
|
|
__be32 consumer_counter;
|
|
__be32 produser_counter;
|
|
u8 rsvd5[16];
|
|
};
|
|
|
|
struct mlx5_create_eq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
u8 rsvd0[3];
|
|
u8 input_eqn;
|
|
u8 rsvd1[4];
|
|
struct mlx5_eq_context ctx;
|
|
u8 rsvd2[8];
|
|
__be64 events_mask;
|
|
u8 rsvd3[176];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_create_eq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd0[3];
|
|
u8 eq_number;
|
|
u8 rsvd1[4];
|
|
};
|
|
|
|
struct mlx5_map_eq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be64 mask;
|
|
u8 mu;
|
|
u8 rsvd0[2];
|
|
u8 eqn;
|
|
u8 rsvd1[24];
|
|
};
|
|
|
|
struct mlx5_map_eq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
struct mlx5_query_eq_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
u8 rsvd0[3];
|
|
u8 eqn;
|
|
u8 rsvd1[4];
|
|
};
|
|
|
|
struct mlx5_query_eq_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
struct mlx5_eq_context ctx;
|
|
};
|
|
|
|
struct mlx5_mkey_seg {
|
|
/* This is a two bit field occupying bits 31-30.
|
|
* bit 31 is always 0,
|
|
* bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
|
|
*/
|
|
u8 status;
|
|
u8 pcie_control;
|
|
u8 flags;
|
|
u8 version;
|
|
__be32 qpn_mkey7_0;
|
|
u8 rsvd1[4];
|
|
__be32 flags_pd;
|
|
__be64 start_addr;
|
|
__be64 len;
|
|
__be32 bsfs_octo_size;
|
|
u8 rsvd2[16];
|
|
__be32 xlt_oct_size;
|
|
u8 rsvd3[3];
|
|
u8 log2_page_size;
|
|
u8 rsvd4[4];
|
|
};
|
|
|
|
struct mlx5_query_special_ctxs_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
struct mlx5_query_special_ctxs_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
__be32 dump_fill_mkey;
|
|
__be32 reserved_lkey;
|
|
};
|
|
|
|
struct mlx5_create_mkey_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 input_mkey_index;
|
|
u8 rsvd0[4];
|
|
struct mlx5_mkey_seg seg;
|
|
u8 rsvd1[16];
|
|
__be32 xlat_oct_act_size;
|
|
__be32 rsvd2;
|
|
u8 rsvd3[168];
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_create_mkey_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
__be32 mkey;
|
|
u8 rsvd[4];
|
|
};
|
|
|
|
struct mlx5_query_mkey_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 mkey;
|
|
};
|
|
|
|
struct mlx5_query_mkey_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_modify_mkey_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 mkey;
|
|
__be64 pas[0];
|
|
};
|
|
|
|
struct mlx5_modify_mkey_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
struct mlx5_dump_mkey_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
};
|
|
|
|
struct mlx5_dump_mkey_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
__be32 mkey;
|
|
};
|
|
|
|
struct mlx5_mad_ifc_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be16 remote_lid;
|
|
u8 rsvd0;
|
|
u8 port;
|
|
u8 rsvd1[4];
|
|
u8 data[256];
|
|
};
|
|
|
|
struct mlx5_mad_ifc_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
u8 data[256];
|
|
};
|
|
|
|
struct mlx5_access_reg_mbox_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
u8 rsvd0[2];
|
|
__be16 register_id;
|
|
__be32 arg;
|
|
__be32 data[0];
|
|
};
|
|
|
|
struct mlx5_access_reg_mbox_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
__be32 data[0];
|
|
};
|
|
|
|
#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
|
|
|
|
enum {
|
|
MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
|
|
};
|
|
|
|
struct mlx5_allocate_psv_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 npsv_pd;
|
|
__be32 rsvd_psv0;
|
|
};
|
|
|
|
struct mlx5_allocate_psv_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
__be32 psv_idx[4];
|
|
};
|
|
|
|
struct mlx5_destroy_psv_in {
|
|
struct mlx5_inbox_hdr hdr;
|
|
__be32 psv_number;
|
|
u8 rsvd[4];
|
|
};
|
|
|
|
struct mlx5_destroy_psv_out {
|
|
struct mlx5_outbox_hdr hdr;
|
|
u8 rsvd[8];
|
|
};
|
|
|
|
#define MLX5_CMD_OP_MAX 0x939
|
|
|
|
enum {
|
|
VPORT_STATE_DOWN = 0x0,
|
|
VPORT_STATE_UP = 0x1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_L3_PROT_TYPE_IPV4 = 0,
|
|
MLX5_L3_PROT_TYPE_IPV6 = 1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_L4_PROT_TYPE_TCP = 0,
|
|
MLX5_L4_PROT_TYPE_UDP = 1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
|
|
MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
|
|
MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
|
|
MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
|
|
MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
|
|
};
|
|
|
|
enum {
|
|
MLX5_MATCH_OUTER_HEADERS = 1 << 0,
|
|
MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
|
|
MLX5_MATCH_INNER_HEADERS = 1 << 2,
|
|
|
|
};
|
|
|
|
enum {
|
|
MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
|
|
MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
|
|
MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
|
|
MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
|
|
};
|
|
|
|
enum {
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
|
|
};
|
|
|
|
enum {
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
|
|
MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
|
|
};
|
|
|
|
enum {
|
|
MLX5_UC_ADDR_CHANGE = (1 << 0),
|
|
MLX5_MC_ADDR_CHANGE = (1 << 1),
|
|
MLX5_VLAN_CHANGE = (1 << 2),
|
|
MLX5_PROMISC_CHANGE = (1 << 3),
|
|
MLX5_MTU_CHANGE = (1 << 4),
|
|
};
|
|
|
|
enum mlx5_list_type {
|
|
MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
|
|
MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
|
|
MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
|
|
};
|
|
|
|
enum {
|
|
MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
|
|
MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
|
|
MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
|
|
};
|
|
|
|
/* MLX5 DEV CAPs */
|
|
|
|
/* TODO: EAT.ME */
|
|
enum mlx5_cap_mode {
|
|
HCA_CAP_OPMOD_GET_MAX = 0,
|
|
HCA_CAP_OPMOD_GET_CUR = 1,
|
|
};
|
|
|
|
enum mlx5_cap_type {
|
|
MLX5_CAP_GENERAL = 0,
|
|
MLX5_CAP_ETHERNET_OFFLOADS,
|
|
MLX5_CAP_ODP,
|
|
MLX5_CAP_ATOMIC,
|
|
MLX5_CAP_ROCE,
|
|
MLX5_CAP_IPOIB_OFFLOADS,
|
|
MLX5_CAP_EOIB_OFFLOADS,
|
|
MLX5_CAP_FLOW_TABLE,
|
|
MLX5_CAP_ESWITCH_FLOW_TABLE,
|
|
MLX5_CAP_ESWITCH,
|
|
/* NUM OF CAP Types */
|
|
MLX5_CAP_NUM
|
|
};
|
|
|
|
/* GET Dev Caps macros */
|
|
#define MLX5_CAP_GEN(mdev, cap) \
|
|
MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
|
|
|
|
#define MLX5_CAP_GEN_MAX(mdev, cap) \
|
|
MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
|
|
|
|
#define MLX5_CAP_ETH(mdev, cap) \
|
|
MLX5_GET(per_protocol_networking_offload_caps,\
|
|
mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
|
|
|
|
#define MLX5_CAP_ETH_MAX(mdev, cap) \
|
|
MLX5_GET(per_protocol_networking_offload_caps,\
|
|
mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
|
|
|
|
#define MLX5_CAP_ROCE(mdev, cap) \
|
|
MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
|
|
|
|
#define MLX5_CAP_ROCE_MAX(mdev, cap) \
|
|
MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
|
|
|
|
#define MLX5_CAP_ATOMIC(mdev, cap) \
|
|
MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
|
|
|
|
#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
|
|
MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE(mdev, cap) \
|
|
MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
|
|
MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
|
|
MLX5_GET(flow_table_eswitch_cap, \
|
|
mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
|
|
MLX5_GET(flow_table_eswitch_cap, \
|
|
mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_EGRESS_ACL(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE(dev, \
|
|
flow_table_properties_esw_acl_egress.cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_EGRESS_ACL_MAX(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE_MAX(dev, \
|
|
flow_table_properties_esw_acl_egress.cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_INGRESS_ACL(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE(dev, \
|
|
flow_table_properties_esw_acl_ingress.cap)
|
|
|
|
#define MLX5_CAP_ESW_FLOWTABLE_INGRESS_ACL_MAX(mdev, cap) \
|
|
MLX5_CAP_ESW_FLOWTABLE_MAX(dev, \
|
|
flow_table_properties_esw_acl_ingress.cap)
|
|
|
|
#define MLX5_CAP_ESW(mdev, cap) \
|
|
MLX5_GET(e_switch_cap, \
|
|
mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
|
|
|
|
#define MLX5_CAP_ESW_MAX(mdev, cap) \
|
|
MLX5_GET(e_switch_cap, \
|
|
mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
|
|
|
|
#define MLX5_CAP_ODP(mdev, cap)\
|
|
MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
|
|
|
|
#define MLX5_CAP_ODP_MAX(mdev, cap)\
|
|
MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
|
|
|
|
enum {
|
|
MLX5_CMD_STAT_OK = 0x0,
|
|
MLX5_CMD_STAT_INT_ERR = 0x1,
|
|
MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
|
|
MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
|
|
MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
|
|
MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
|
|
MLX5_CMD_STAT_RES_BUSY = 0x6,
|
|
MLX5_CMD_STAT_LIM_ERR = 0x8,
|
|
MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
|
|
MLX5_CMD_STAT_IX_ERR = 0xa,
|
|
MLX5_CMD_STAT_NO_RES_ERR = 0xf,
|
|
MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
|
|
MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
|
|
MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
|
|
MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
|
|
MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
|
|
};
|
|
|
|
enum {
|
|
MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
|
|
MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
|
|
MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
|
|
MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
|
|
MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
|
|
MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
|
|
MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
|
|
MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
|
|
};
|
|
|
|
enum {
|
|
MLX5_CAP_PORT_TYPE_IB = 0x0,
|
|
MLX5_CAP_PORT_TYPE_ETH = 0x1,
|
|
};
|
|
|
|
enum {
|
|
MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
|
|
MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
|
|
MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
|
|
};
|
|
|
|
enum {
|
|
MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
|
|
};
|
|
|
|
static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
|
|
{
|
|
if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
|
|
return 0;
|
|
return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
|
|
}
|
|
|
|
struct mlx5_ifc_mcia_reg_bits {
|
|
u8 l[0x1];
|
|
u8 reserved_0[0x7];
|
|
u8 module[0x8];
|
|
u8 reserved_1[0x8];
|
|
u8 status[0x8];
|
|
|
|
u8 i2c_device_address[0x8];
|
|
u8 page_number[0x8];
|
|
u8 device_address[0x10];
|
|
|
|
u8 reserved_2[0x10];
|
|
u8 size[0x10];
|
|
|
|
u8 reserved_3[0x20];
|
|
|
|
u8 dword_0[0x20];
|
|
u8 dword_1[0x20];
|
|
u8 dword_2[0x20];
|
|
u8 dword_3[0x20];
|
|
u8 dword_4[0x20];
|
|
u8 dword_5[0x20];
|
|
u8 dword_6[0x20];
|
|
u8 dword_7[0x20];
|
|
u8 dword_8[0x20];
|
|
u8 dword_9[0x20];
|
|
u8 dword_10[0x20];
|
|
u8 dword_11[0x20];
|
|
};
|
|
|
|
#define MLX5_CMD_OP_QUERY_EEPROM 0x93c
|
|
|
|
struct mlx5_mini_cqe8 {
|
|
union {
|
|
u32 rx_hash_result;
|
|
u32 checksum;
|
|
struct {
|
|
u16 wqe_counter;
|
|
u8 s_wqe_opcode;
|
|
u8 reserved;
|
|
} s_wqe_info;
|
|
};
|
|
u32 byte_cnt;
|
|
};
|
|
|
|
enum {
|
|
MLX5_NO_INLINE_DATA,
|
|
MLX5_INLINE_DATA32_SEG,
|
|
MLX5_INLINE_DATA64_SEG,
|
|
MLX5_COMPRESSED,
|
|
};
|
|
|
|
enum mlx5_exp_cqe_zip_recv_type {
|
|
MLX5_CQE_FORMAT_HASH,
|
|
MLX5_CQE_FORMAT_CSUM,
|
|
};
|
|
|
|
#define MLX5E_CQE_FORMAT_MASK 0xc
|
|
static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
|
|
{
|
|
return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
|
|
}
|
|
|
|
#endif /* MLX5_DEVICE_H */
|