d64c132e24
o Eliminate IA64_PHYS_TO_RR6 and change all places where the macro is used
by calling either bus_space_map() or pmap_mapdev().
o Implement bus_space_map() in terms of pmap_mapdev() and implement
bus_space_unmap() in terms of pmap_unmapdev().
o Have ia64_pib hold the uncached virtual address of the processor interrupt
block throughout the kernel's life and access the elements of the PIB
through this structure pointer.
This is a non-functional change with the exception of using ia64_ld1() and
ia64_st8() to write to the PIB. We were still using assignments, for which
the compiler generates semaphore reads -- which cause undefined behaviour
for uncacheable memory. Note also that the memory barriers in ipi_send() are
critical for proper functioning.
With all the mapping of uncached memory done by pmap_mapdev(), we can keep
track of the translations and wire them in the CPU. This then eliminates
the need to reserve a whole region for uncached I/O and it eliminates
translation traps for device I/O accesses.
248 lines
6.7 KiB
C
248 lines
6.7 KiB
C
/*-
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* Copyright (c) 2001 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/actables.h>
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#include <machine/md_var.h>
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struct sapic *sapic_create(int, int, u_int64_t);
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static void
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print_entry(ACPI_SUBTABLE_HEADER *entry)
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{
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switch (entry->Type) {
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case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE: {
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ACPI_MADT_INTERRUPT_OVERRIDE *iso =
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(ACPI_MADT_INTERRUPT_OVERRIDE *)entry;
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printf("\tInterrupt source override entry\n");
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printf("\t\tBus=%u, Source=%u, Irq=0x%x\n", iso->Bus,
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iso->SourceIrq, iso->GlobalIrq);
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break;
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}
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case ACPI_MADT_TYPE_IO_APIC:
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printf("\tI/O APIC entry\n");
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break;
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case ACPI_MADT_TYPE_IO_SAPIC: {
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ACPI_MADT_IO_SAPIC *sapic = (ACPI_MADT_IO_SAPIC *)entry;
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printf("\tI/O SAPIC entry\n");
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printf("\t\tId=0x%x, InterruptBase=0x%x, Address=0x%lx\n",
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sapic->Id, sapic->GlobalIrqBase, sapic->Address);
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break;
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}
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case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
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printf("\tLocal APIC NMI entry\n");
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break;
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case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE: {
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ACPI_MADT_LOCAL_APIC_OVERRIDE *lapic =
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(ACPI_MADT_LOCAL_APIC_OVERRIDE *)entry;
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printf("\tLocal APIC override entry\n");
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printf("\t\tLocal APIC address=0x%jx\n", lapic->Address);
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break;
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}
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case ACPI_MADT_TYPE_LOCAL_SAPIC: {
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ACPI_MADT_LOCAL_SAPIC *sapic = (ACPI_MADT_LOCAL_SAPIC *)entry;
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printf("\tLocal SAPIC entry\n");
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printf("\t\tProcessorId=0x%x, Id=0x%x, Eid=0x%x",
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sapic->ProcessorId, sapic->Id, sapic->Eid);
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if (!(sapic->LapicFlags & ACPI_MADT_ENABLED))
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printf(" (disabled)");
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printf("\n");
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break;
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}
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case ACPI_MADT_TYPE_NMI_SOURCE:
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printf("\tNMI entry\n");
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break;
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case ACPI_MADT_TYPE_INTERRUPT_SOURCE: {
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ACPI_MADT_INTERRUPT_SOURCE *pis =
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(ACPI_MADT_INTERRUPT_SOURCE *)entry;
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printf("\tPlatform interrupt entry\n");
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printf("\t\tPolarity=%u, TriggerMode=%u, Id=0x%x, "
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"Eid=0x%x, Vector=0x%x, Irq=%d\n",
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pis->IntiFlags & ACPI_MADT_POLARITY_MASK,
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(pis->IntiFlags & ACPI_MADT_TRIGGER_MASK) >> 2,
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pis->Id, pis->Eid, pis->IoSapicVector, pis->GlobalIrq);
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break;
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}
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case ACPI_MADT_TYPE_LOCAL_APIC:
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printf("\tLocal APIC entry\n");
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break;
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default:
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printf("\tUnknown type %d entry\n", entry->Type);
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break;
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}
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}
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void
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ia64_probe_sapics(void)
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{
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ACPI_PHYSICAL_ADDRESS rsdp_ptr;
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ACPI_SUBTABLE_HEADER *entry;
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ACPI_TABLE_MADT *table;
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ACPI_TABLE_RSDP *rsdp;
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ACPI_TABLE_XSDT *xsdt;
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char *end, *p;
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int t, tables;
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if ((rsdp_ptr = AcpiOsGetRootPointer()) == 0)
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return;
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rsdp = (ACPI_TABLE_RSDP *)IA64_PHYS_TO_RR7(rsdp_ptr);
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xsdt = (ACPI_TABLE_XSDT *)IA64_PHYS_TO_RR7(rsdp->XsdtPhysicalAddress);
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tables = (UINT64 *)((char *)xsdt + xsdt->Header.Length) -
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xsdt->TableOffsetEntry;
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for (t = 0; t < tables; t++) {
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table = (ACPI_TABLE_MADT *)
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IA64_PHYS_TO_RR7(xsdt->TableOffsetEntry[t]);
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if (bootverbose)
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printf("Table '%c%c%c%c' at %p\n",
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table->Header.Signature[0],
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table->Header.Signature[1],
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table->Header.Signature[2],
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table->Header.Signature[3], table);
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if (strncmp(table->Header.Signature, ACPI_SIG_MADT,
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ACPI_NAME_SIZE) != 0 ||
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ACPI_FAILURE(AcpiTbChecksum((void *)table,
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table->Header.Length)))
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continue;
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/* Save the address of the processor interrupt block. */
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if (bootverbose)
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printf("\tLocal APIC address=0x%x\n", table->Address);
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ia64_lapic_addr = table->Address;
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end = (char *)table + table->Header.Length;
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p = (char *)(table + 1);
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while (p < end) {
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entry = (ACPI_SUBTABLE_HEADER *)p;
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if (bootverbose)
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print_entry(entry);
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switch (entry->Type) {
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case ACPI_MADT_TYPE_IO_SAPIC: {
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ACPI_MADT_IO_SAPIC *sapic =
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(ACPI_MADT_IO_SAPIC *)entry;
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sapic_create(sapic->Id, sapic->GlobalIrqBase,
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sapic->Address);
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break;
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}
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case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE: {
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ACPI_MADT_LOCAL_APIC_OVERRIDE *lapic =
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(ACPI_MADT_LOCAL_APIC_OVERRIDE *)entry;
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ia64_lapic_addr = lapic->Address;
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break;
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}
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#ifdef SMP
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case ACPI_MADT_TYPE_LOCAL_SAPIC: {
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ACPI_MADT_LOCAL_SAPIC *sapic =
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(ACPI_MADT_LOCAL_SAPIC *)entry;
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if (sapic->LapicFlags & ACPI_MADT_ENABLED)
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cpu_mp_add(sapic->ProcessorId,
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sapic->Id, sapic->Eid);
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break;
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}
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#endif
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default:
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break;
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}
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p += entry->Length;
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}
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}
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}
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/*
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* Count the number of local SAPIC entries in the APIC table. Every enabled
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* entry corresponds to a processor.
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*/
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int
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ia64_count_cpus(void)
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{
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ACPI_PHYSICAL_ADDRESS rsdp_ptr;
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ACPI_MADT_LOCAL_SAPIC *entry;
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ACPI_TABLE_MADT *table;
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ACPI_TABLE_RSDP *rsdp;
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ACPI_TABLE_XSDT *xsdt;
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char *end, *p;
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int cpus, t, tables;
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if ((rsdp_ptr = AcpiOsGetRootPointer()) == 0)
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return (0);
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rsdp = (ACPI_TABLE_RSDP *)IA64_PHYS_TO_RR7(rsdp_ptr);
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xsdt = (ACPI_TABLE_XSDT *)IA64_PHYS_TO_RR7(rsdp->XsdtPhysicalAddress);
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tables = (UINT64 *)((char *)xsdt + xsdt->Header.Length) -
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xsdt->TableOffsetEntry;
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cpus = 0;
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for (t = 0; t < tables; t++) {
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table = (ACPI_TABLE_MADT *)
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IA64_PHYS_TO_RR7(xsdt->TableOffsetEntry[t]);
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if (strncmp(table->Header.Signature, ACPI_SIG_MADT,
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ACPI_NAME_SIZE) != 0 ||
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ACPI_FAILURE(AcpiTbChecksum((void *)table,
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table->Header.Length)))
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continue;
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end = (char *)table + table->Header.Length;
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p = (char *)(table + 1);
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while (p < end) {
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entry = (ACPI_MADT_LOCAL_SAPIC *)p;
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if (entry->Header.Type == ACPI_MADT_TYPE_LOCAL_SAPIC &&
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(entry->LapicFlags & ACPI_MADT_ENABLED))
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cpus++;
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p += entry->Header.Length;
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}
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}
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return (cpus);
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}
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