ian fcebee2f66 Update the imx5/imx6 cpu_reset() implementation based on a new understanding ... of the SRS (software reset) bit in the watchdog control register. Despite what the manual seems to imply, this bit DOES trigger an immediate reset, as opposed to simply flagging the type of reset as software-triggered.		2015-11-21 23:30:47 +00:00
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imx	Update the imx5/imx6 cpu_reset() implementation based on a new understanding	2015-11-21 23:30:47 +00:00
vybrid	Create device options for the two common ARM timers.	2015-11-21 16:23:56 +00:00
fsl_ocotp.c	The ocotp driver provides access to registers containing chip configuration	2014-09-02 02:54:55 +00:00
fsl_ocotpreg.h
fsl_ocotpvar.h