478 lines
18 KiB
Plaintext
478 lines
18 KiB
Plaintext
# Chelsio T5 Factory Default configuration file.
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#
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# Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
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#
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# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
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# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
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# IN PHYSICAL DAMAGE TO T4 ADAPTERS.
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# This file provides the default, power-on configuration for 4-port T4-based
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# adapters shipped from the factory. These defaults are designed to address
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# the needs of the vast majority of T4 customers. The basic idea is to have
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# a default configuration which allows a customer to plug a T4 adapter in and
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# have it work regardless of OS, driver or application except in the most
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# unusual and/or demanding customer applications.
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#
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# Many of the T4 resources which are described by this configuration are
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# finite. This requires balancing the configuration/operation needs of
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# device drivers across OSes and a large number of customer application.
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#
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# Some of the more important resources to allocate and their constaints are:
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# 1. Virtual Interfaces: 128.
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# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
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# must use a power of 2 Ingress Queues.
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# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
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# power of 2 Egress Queues.
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# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
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# Virtual Functions based off of a Physical Function all get the
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# same umber of MSI-X Vectors as the base Physical Function.
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# Additionally, regardless of whether Virtual Functions are enabled or
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# not, their MSI-X "needs" are counted by the PCI-E implementation.
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# And finally, all Physical Funcations capable of supporting Virtual
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# Functions (PF0-3) must have the same number of configured TotalVFs in
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# their SR-IOV Capabilities.
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# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
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# address matching on Ingress Packets.
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#
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# Some of the important OS/Driver resource needs are:
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# 6. Some OS Drivers will manage all resources through a single Physical
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# Function (currently PF0 but it could be any Physical Function). Thus,
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# this "Unified PF" will need to have enough resources allocated to it
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# to allow for this. And because of the MSI-X resource allocation
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# constraints mentioned above, this probably means we'll either have to
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# severely limit the TotalVFs if we continue to use PF0 as the Unified PF
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# or we'll need to move the Unified PF into the PF4-7 range since those
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# Physical Functions don't have any Virtual Functions associated with
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# them.
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# 7. Some OS Drivers will manage different ports and functions (NIC,
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# storage, etc.) on different Physical Functions. For example, NIC
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# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
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#
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# Some of the customer application needs which need to be accommodated:
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# 8. Some customers will want to support large CPU count systems with
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# good scaling. Thus, we'll need to accommodate a number of
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# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
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# to be involved per port and per application function. For example,
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# in the case where all ports and application functions will be
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# managed via a single Unified PF and we want to accommodate scaling up
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# to 8 CPUs, we would want:
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#
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# 4 ports *
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# 3 application functions (NIC, FCoE, iSCSI) per port *
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# 8 Ingress Queue/MSI-X Vectors per application function
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#
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# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
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# (Plus a few for Firmware Event Queues, etc.)
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#
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# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
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# Virtual Machines to directly access T4 functionality via SR-IOV
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# Virtual Functions and "PCI Device Passthrough" -- this is especially
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# true for the NIC application functionality. (Note that there is
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# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual
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# Functions so this is in fact solely limited to NIC.)
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#
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# Global configuration settings.
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#
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[global]
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rss_glb_config_mode = basicvirtual
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rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
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# PCIE_MA_RSP register
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pcie_ma_rsp_timervalue = 500 # the timer value in units of us
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reg[0x59c4] = 0x3/0x3 # enable the timers
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# PL_TIMEOUT register
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pl_timeout_value = 200 # the timeout value in units of us
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# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
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# Page Size and a 64B L1 Cache Line Size. It programs the
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# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
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# If a Master PF Driver finds itself on a machine with different
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# parameters, then the Master PF Driver is responsible for initializing
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# these parameters to appropriate values.
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#
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# Notes:
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# 1. The Free List Buffer Sizes below are raw and the firmware will
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# round them up to the Ingress Padding Boundary.
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# 2. The SGE Timer Values below are expressed below in microseconds.
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# The firmware will convert these values to Core Clock Ticks when
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# it processes the configuration parameters.
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#
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reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
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reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
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reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
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reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
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reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
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reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
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reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
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reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
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reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
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reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
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reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
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reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
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reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
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reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
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# SGE_THROTTLE_CONTROL
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bar2throttlecount = 500 # bar2throttlecount in us
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sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
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reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
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# SGE_VFIFO_SIZE is not set, then
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# firmware will set it up in function
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# of number of egress queues used
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reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
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# threshold set to queue depth
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# minus 128-entries for FL and HP
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# queues, and 0xfff for LP which
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# prompts the firmware to set it up
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# in function of egress queues
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# used
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reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
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# prompts the firmware to set it up in
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# function of number of egress queues
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# used
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reg[0x7dc0] = 0x062f8849 # TP_SHIFT_CNT
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# Selection of tuples for LE filter lookup, fields (and widths which
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# must sum to <= 36): { IP Fragment (1), MPS Match Type (3),
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# IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) }
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#
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe, srvrsram
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP RX payload
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tp_pmrx = 30, 512
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# TP RX payload page size
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tp_pmrx_pagesize = 64K
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# TP number of RX channels
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tp_nrxch = 0 # 0 (auto) = 1
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# Percentage of dynamic memory (in either the EDRAM or external MEM)
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# to use for TP TX payload
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tp_pmtx = 50, 512
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# TP TX payload page size
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tp_pmtx_pagesize = 64K
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# TP number of TX channels
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tp_ntxch = 0 # 0 (auto) = equal number of ports
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reg[0x19c04] = 0x00400000/0x00400000 # LE Server SRAM Enable
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# Some "definitions" to make the rest of this a bit more readable. We support
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# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
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# per function per port ...
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#
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# NMSIX = 1088 # available MSI-X Vectors
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# NVI = 128 # available Virtual Interfaces
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# NMPSTCAM = 336 # MPS TCAM entries
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#
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# NPORTS = 4 # ports
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# NCPUS = 8 # CPUs we want to support scalably
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# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
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# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
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# PF" which many OS Drivers will use to manage most or all functions.
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#
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# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
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# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
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# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
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# will be specified as the "Ingress Queue Asynchronous Destination Index."
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# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
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# than or equal to the number of Ingress Queues ...
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#
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# NVI_NIC = 4 # NIC access to NPORTS
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# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
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# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
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# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
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# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
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# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
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#
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# NVI_OFLD = 0 # Offload uses NIC function to access ports
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# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
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# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
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# NEQ_OFLD = 16 # Offload Egress Queues (FL)
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# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
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# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
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#
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# NVI_RDMA = 0 # RDMA uses NIC function to access ports
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# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
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# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
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# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
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# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
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# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
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#
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# NEQ_WD = 128 # Wire Direct TX Queues and FLs
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# NETHCTRL_WD = 64 # Wire Direct TX Queues
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# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
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#
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# NVI_ISCSI = 4 # ISCSI access to NPORTS
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# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
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# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
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# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
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# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
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# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
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#
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# NVI_FCOE = 4 # FCOE access to NPORTS
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# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
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# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
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# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
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# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
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# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
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# Two extra Ingress Queues per function for Firmware Events and Forwarded
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# Interrupts, and two extra interrupts per function for Firmware Events (or a
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# Forwarded Interrupt Queue) and General Interrupts per function.
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#
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# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
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# # Forwarded Interrupts
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# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
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# # General Interrupts
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# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
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# their interrupts forwarded to another set of Forwarded Interrupt Queues.
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#
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# NVI_HYPERV = 16 # VMs we want to support
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# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
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# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
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# NEQ_HYPERV = 32 # VIQs Free Lists
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# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
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# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
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# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
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# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
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#
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# NVI_UNIFIED = 28
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# NFLIQ_UNIFIED = 106
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# NETHCTRL_UNIFIED = 32
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# NEQ_UNIFIED = 124
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# NMPSTCAM_UNIFIED = 40
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#
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# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
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# that up to 128 to make sure the Unified PF doesn't run out of resources.
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#
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# NMSIX_UNIFIED = 128
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#
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# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
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# which is 34 but they're probably safe with 32.
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#
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# NMSIX_STORAGE = 32
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# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
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# associated with it. Thus, the MSI-X Vector allocations we give to the
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# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
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# provision many more Virtual Functions than we can if the UnifiedPF were
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# one of PF0-3.
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#
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# All of the below PCI-E parameters are actually stored in various *_init.txt
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# files. We include them below essentially as comments.
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#
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# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
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# ports 0-3.
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#
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# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
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#
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# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
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# storage applications across all four possible ports.
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#
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# Additionally, since the UnifiedPF isn't one of the per-port Physical
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# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
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# different PCI Device IDs which will allow Unified and Per-Port Drivers
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# to directly select the type of Physical Function to which they wish to be
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# attached.
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#
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# Note that the actual values used for the PCI-E Intelectual Property will be
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# 1 less than those below since that's the way it "counts" things. For
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# readability, we use the number we actually mean ...
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#
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# PF0_INT = 8 # NCPUS
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# PF1_INT = 8 # NCPUS
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# PF2_INT = 8 # NCPUS
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# PF3_INT = 8 # NCPUS
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# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
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#
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# PF4_INT = 128 # NMSIX_UNIFIED
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# PF5_INT = 32 # NMSIX_STORAGE
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# PF6_INT = 32 # NMSIX_STORAGE
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# PF7_INT = 0 # Nothing Assigned
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# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
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#
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# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
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#
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# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
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# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
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#
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# NVF = 16
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# For those OSes which manage different ports on different PFs, we need
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# only enough resources to support a single port's NIC application functions
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# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
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# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
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# managed on the "storage PFs" (see below).
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#
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# Some OS Drivers manage all application functions for all ports via PF4.
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# Thus we need to provide a large number of resources here. For Egress
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# Queues we need to account for both TX Queues as well as Free List Queues
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# (because the host is responsible for producing Free List Buffers for the
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# hardware to consume).
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#
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[function "0"]
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wx_caps = all # write/execute permissions for all commands
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r_caps = all # read permissions for all commands
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nvi = 28 # NVI_UNIFIED
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niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
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nethctrl = 96 # NETHCTRL_UNIFIED + NETHCTRL_WD
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neq = 252 # NEQ_UNIFIED + NEQ_WD
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nexactf = 40 # NMPSTCAM_UNIFIED
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nroute = 32 # number of routing region entries
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nclip = 32 # number of clip region entries
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nfilter = 48 # number of filter region entries
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nserver = 32 # number of server region entries
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nhash = 2048 # number of hash region entries
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protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
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tp_l2t = 3072
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tp_ddp = 2
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tp_ddp_iscsi = 2
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tp_stag = 2
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tp_pbl = 5
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tp_rq = 7
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# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
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# need to have Virtual Interfaces on each of the four ports with up to NCPUS
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# "Queue Sets" each.
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#
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[function "1"]
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wx_caps = all # write/execute permissions for all commands
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r_caps = all # read permissions for all commands
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nvi = 4 # NPORTS
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niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
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nethctrl = 32 # NPORTS*NCPUS
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neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
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nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
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# which is OK since < MIN(SUM PF0..3, PF4)
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# and we never load PF0..3 and PF4 concurrently
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nhash = 2048
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protocol = fcoe_initiator
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tp_ddp = 2
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fcoe_nfcf = 16
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fcoe_nvnp = 32
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fcoe_nssn = 1024
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# The following function, 1023, is not an actual PCIE function but is used to
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# configure and reserve firmware internal resources that come from the global
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# resource pool.
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#
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[function "1023"]
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wx_caps = all # write/execute permissions for all commands
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r_caps = all # read permissions for all commands
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nvi = 4 # NVI_UNIFIED
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cmask = all # access to all channels
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pmask = all # access to all four ports ...
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nexactf = 8 # NPORTS + DCBX +
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nfilter = 16 # number of filter region entries
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# For Virtual functions, we only allow NIC functionality and we only allow
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# access to one port (1 << PF). Note that because of limitations in the
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# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
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# and GTS registers, the number of Ingress and Egress Queues must be a power
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# of 2.
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#
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[function "0/*"] # NVF
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wx_caps = 0x82 # DMAQ | VF
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r_caps = 0x86 # DMAQ | VF | PORT
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nvi = 1 # 1 port
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niqflint = 4 # 2 "Queue Sets" + NXIQ
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nethctrl = 2 # 2 "Queue Sets"
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neq = 4 # 2 "Queue Sets" * 2
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nexactf = 4
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cmask = all # access to all channels
|
|
pmask = 0x1 # access to only one port ...
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|
|
|
[function "1/*"] # NVF
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|
wx_caps = 0x82 # DMAQ | VF
|
|
r_caps = 0x86 # DMAQ | VF | PORT
|
|
nvi = 1 # 1 port
|
|
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
|
nethctrl = 2 # 2 "Queue Sets"
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|
neq = 4 # 2 "Queue Sets" * 2
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|
nexactf = 4
|
|
cmask = all # access to all channels
|
|
pmask = 0x2 # access to only one port ...
|
|
|
|
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
|
|
# for packets from the wire as well as the loopback path of the L2 switch. The
|
|
# folling params control how the buffer memory is distributed and the L2 flow
|
|
# control settings:
|
|
#
|
|
# bg_mem: %-age of mem to use for port/buffer group
|
|
# lpbk_mem: %-age of port/bg mem to use for loopback
|
|
# hwm: high watermark; bytes available when starting to send pause
|
|
# frames (in units of 0.1 MTU)
|
|
# lwm: low watermark; bytes remaining when sending 'unpause' frame
|
|
# (in inuits of 0.1 MTU)
|
|
# dwm: minimum delta between high and low watermark (in units of 100
|
|
# Bytes)
|
|
#
|
|
[port "0"]
|
|
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
|
|
bg_mem = 25
|
|
lpbk_mem = 25
|
|
hwm = 30
|
|
lwm = 15
|
|
dwm = 30
|
|
|
|
[port "1"]
|
|
dcb = ppp, dcbx
|
|
bg_mem = 25
|
|
lpbk_mem = 25
|
|
hwm = 30
|
|
lwm = 15
|
|
dwm = 30
|
|
|
|
[port "2"]
|
|
dcb = ppp, dcbx
|
|
bg_mem = 25
|
|
lpbk_mem = 25
|
|
hwm = 30
|
|
lwm = 15
|
|
dwm = 30
|
|
|
|
[port "3"]
|
|
dcb = ppp, dcbx
|
|
bg_mem = 25
|
|
lpbk_mem = 25
|
|
hwm = 30
|
|
lwm = 15
|
|
dwm = 30
|
|
|
|
[fini]
|
|
version = 0x1425000d
|
|
checksum = 0x22f1530b
|
|
|
|
# Total resources used by above allocations:
|
|
# Virtual Interfaces: 104
|
|
# Ingress Queues/w Free Lists and Interrupts: 526
|
|
# Egress Queues: 702
|
|
# MPS TCAM Entries: 336
|
|
# MSI-X Vectors: 736
|
|
# Virtual Functions: 64
|
|
#
|
|
# $FreeBSD$
|
|
#
|