1537078d8f
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367 lines
13 KiB
C
367 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*
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* Definitions for the Marvell 88W8363 Wireless LAN controller.
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*/
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#ifndef _DEV_MWL_MVVAR_H
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#define _DEV_MWL_MVVAR_H
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#include <sys/endian.h>
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#include <sys/bus.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/mwl/mwlhal.h>
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#include <dev/mwl/mwlreg.h>
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#include <dev/mwl/if_mwlioctl.h>
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#ifndef MWL_TXBUF
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#define MWL_TXBUF 256 /* number of TX descriptors/buffers */
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#endif
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#ifndef MWL_TXACKBUF
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#define MWL_TXACKBUF (MWL_TXBUF/2) /* number of TX ACK desc's/buffers */
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#endif
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#ifndef MWL_RXDESC
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#define MWL_RXDESC 256 /* number of RX descriptors */
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#endif
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#ifndef MWL_RXBUF
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#define MWL_RXBUF ((5*MWL_RXDESC)/2)/* number of RX dma buffers */
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#endif
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#ifndef MWL_MAXBA
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#define MWL_MAXBA 2 /* max BA streams/sta */
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#endif
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#ifdef MWL_SGDMA_SUPPORT
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#define MWL_TXDESC 6 /* max tx descriptors/segments */
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#else
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#define MWL_TXDESC 1 /* max tx descriptors/segments */
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#endif
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#ifndef MWL_AGGR_SIZE
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#define MWL_AGGR_SIZE 3839 /* max tx aggregation size */
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#endif
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#define MWL_AGEINTERVAL 1 /* poke f/w every sec to age q's */
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#define MWL_MAXSTAID 64 /* max of 64 stations */
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/*
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* DMA state for tx/rx descriptors.
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*/
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/*
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* Software backed version of tx/rx descriptors. We keep
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* the software state out of the h/w descriptor structure
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* so that may be allocated in uncached memory w/o paying
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* performance hit.
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*/
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struct mwl_txbuf {
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STAILQ_ENTRY(mwl_txbuf) bf_list;
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void *bf_desc; /* h/w descriptor */
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bus_addr_t bf_daddr; /* physical addr of desc */
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bus_dmamap_t bf_dmamap; /* DMA map for descriptors */
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int bf_nseg;
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bus_dma_segment_t bf_segs[MWL_TXDESC];
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struct mbuf *bf_m;
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struct ieee80211_node *bf_node;
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struct mwl_txq *bf_txq; /* backpointer to tx q/ring */
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};
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typedef STAILQ_HEAD(, mwl_txbuf) mwl_txbufhead;
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/*
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* Common "base class" for tx/rx descriptor resources
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* allocated using the bus dma api.
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*/
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struct mwl_descdma {
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const char* dd_name;
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void *dd_desc; /* descriptors */
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bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
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bus_size_t dd_desc_len; /* size of dd_desc */
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bus_dma_segment_t dd_dseg;
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int dd_dnseg; /* number of segments */
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bus_dma_tag_t dd_dmat; /* bus DMA tag */
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bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
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void *dd_bufptr; /* associated buffers */
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};
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/*
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* TX/RX ring definitions. There are 4 tx rings, one
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* per AC, and 1 rx ring. Note carefully that transmit
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* descriptors are treated as a contiguous chunk and the
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* firmware pre-fetches descriptors. This means that we
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* must preserve order when moving descriptors between
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* the active+free lists; otherwise we may stall transmit.
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*/
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struct mwl_txq {
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struct mwl_descdma dma; /* bus dma resources */
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struct mtx lock; /* tx q lock */
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char name[12]; /* e.g. "mwl0_txq4" */
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int qnum; /* f/w q number */
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int txpri; /* f/w tx priority */
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int nfree; /* # buffers on free list */
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mwl_txbufhead free; /* queue of free buffers */
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mwl_txbufhead active; /* queue of active buffers */
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};
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#define MWL_TXQ_LOCK_INIT(_sc, _tq) do { \
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snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \
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device_get_nameunit((_sc)->sc_dev), (_tq)->qnum); \
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mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \
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} while (0)
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#define MWL_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->lock)
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#define MWL_TXQ_LOCK(_tq) mtx_lock(&(_tq)->lock)
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#define MWL_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->lock)
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#define MWL_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED)
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#define MWL_TXDESC_SYNC(txq, ds, how) do { \
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bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \
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} while(0)
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/*
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* RX dma buffers that are not in use are kept on a list.
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*/
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struct mwl_jumbo {
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SLIST_ENTRY(mwl_jumbo) next;
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};
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typedef SLIST_HEAD(, mwl_jumbo) mwl_jumbohead;
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#define MWL_JUMBO_DATA2BUF(_data) ((struct mwl_jumbo *)(_data))
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#define MWL_JUMBO_BUF2DATA(_buf) ((uint8_t *)(_buf))
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#define MWL_JUMBO_OFFSET(_sc, _data) \
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(((const uint8_t *)(_data)) - (const uint8_t *)((_sc)->sc_rxmem))
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#define MWL_JUMBO_DMA_ADDR(_sc, _data) \
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((_sc)->sc_rxmem_paddr + MWL_JUMBO_OFFSET(_sc, _data))
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struct mwl_rxbuf {
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STAILQ_ENTRY(mwl_rxbuf) bf_list;
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void *bf_desc; /* h/w descriptor */
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bus_addr_t bf_daddr; /* physical addr of desc */
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uint8_t *bf_data; /* rx data area */
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};
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typedef STAILQ_HEAD(, mwl_rxbuf) mwl_rxbufhead;
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#define MWL_RXDESC_SYNC(sc, ds, how) do { \
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bus_dmamap_sync((sc)->sc_rxdma.dd_dmat, (sc)->sc_rxdma.dd_dmamap, how);\
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} while (0)
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/*
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* BA stream state. One of these is setup for each stream
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* allocated/created for use. We pre-allocate the h/w stream
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* before sending ADDBA request then complete the setup when
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* get ADDBA response (success). The completed state is setup
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* to optimize the fast path in mwl_txstart--we precalculate
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* the QoS control bits in the outbound frame and use those
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* to identify which BA stream to use (assigning the h/w q to
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* the TxPriority field of the descriptor).
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*
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* NB: Each station may have at most MWL_MAXBA streams at one time.
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*/
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struct mwl_bastate {
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uint16_t qos; /* QoS ctl for BA stream */
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uint8_t txq; /* h/w q for BA stream */
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const MWL_HAL_BASTREAM *bastream; /* A-MPDU BA stream */
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};
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static __inline__ void
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mwl_bastream_setup(struct mwl_bastate *bas, int tid, int txq)
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{
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bas->txq = txq;
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bas->qos = htole16(tid | IEEE80211_QOS_ACKPOLICY_BA);
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}
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static __inline__ void
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mwl_bastream_free(struct mwl_bastate *bas)
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{
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bas->qos = 0;
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bas->bastream = NULL;
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/* NB: don't need to clear txq */
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}
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/*
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* Check the QoS control bits from an outbound frame against the
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* value calculated when a BA stream is setup (above). We need
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* to match the TID and also the ACK policy so we only match AMPDU
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* frames. The bits from the frame are assumed in network byte
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* order, hence the potential byte swap.
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*/
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static __inline__ int
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mwl_bastream_match(const struct mwl_bastate *bas, uint16_t qos)
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{
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return (qos & htole16(IEEE80211_QOS_TID|IEEE80211_QOS_ACKPOLICY)) ==
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bas->qos;
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}
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/* driver-specific node state */
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struct mwl_node {
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struct ieee80211_node mn_node; /* base class */
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struct mwl_ant_info mn_ai; /* antenna info */
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uint32_t mn_avgrssi; /* average rssi over all rx frames */
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uint16_t mn_staid; /* firmware station id */
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struct mwl_bastate mn_ba[MWL_MAXBA];
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struct mwl_hal_vap *mn_hvap; /* hal vap handle */
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};
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#define MWL_NODE(ni) ((struct mwl_node *)(ni))
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#define MWL_NODE_CONST(ni) ((const struct mwl_node *)(ni))
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/*
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* Driver-specific vap state.
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*/
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struct mwl_vap {
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struct ieee80211vap mv_vap; /* base class */
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struct mwl_hal_vap *mv_hvap; /* hal vap handle */
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struct mwl_hal_vap *mv_ap_hvap; /* ap hal vap handle for wds */
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uint16_t mv_last_ps_sta; /* last count of ps sta's */
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uint16_t mv_eapolformat; /* fixed tx rate for EAPOL */
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int (*mv_newstate)(struct ieee80211vap *,
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enum ieee80211_state, int);
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int (*mv_set_tim)(struct ieee80211_node *, int);
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};
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#define MWL_VAP(vap) ((struct mwl_vap *)(vap))
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#define MWL_VAP_CONST(vap) ((const struct mwl_vap *)(vap))
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struct mwl_softc {
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struct ieee80211com sc_ic;
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struct mbufq sc_snd;
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struct mwl_stats sc_stats; /* interface statistics */
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int sc_debug;
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device_t sc_dev;
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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bus_space_handle_t sc_io0h; /* BAR 0 */
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bus_space_tag_t sc_io0t;
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bus_space_handle_t sc_io1h; /* BAR 1 */
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bus_space_tag_t sc_io1t;
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struct mtx sc_mtx; /* master lock (recursive) */
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struct taskqueue *sc_tq; /* private task queue */
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struct callout sc_watchdog;
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int sc_tx_timer;
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unsigned int sc_running : 1,
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sc_invalid : 1, /* disable hardware accesses */
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sc_recvsetup:1, /* recv setup */
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sc_csapending:1,/* 11h channel switch pending */
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sc_radarena : 1,/* radar detection enabled */
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sc_rxblocked: 1;/* rx waiting for dma buffers */
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struct mwl_hal *sc_mh; /* h/w access layer */
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struct mwl_hal_vap *sc_hvap; /* hal vap handle */
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struct mwl_hal_hwspec sc_hwspecs; /* h/w capabilities */
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uint32_t sc_fwrelease; /* release # of loaded f/w */
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struct mwl_hal_txrxdma sc_hwdma; /* h/w dma setup */
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uint32_t sc_imask; /* interrupt mask copy */
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enum ieee80211_phymode sc_curmode;
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u_int16_t sc_curaid; /* current association id */
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u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
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MWL_HAL_CHANNEL sc_curchan;
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MWL_HAL_TXRATE_HANDLING sc_txratehandling;
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u_int16_t sc_rxantenna; /* rx antenna */
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u_int16_t sc_txantenna; /* tx antenna */
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uint8_t sc_napvaps; /* # ap mode vaps */
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uint8_t sc_nwdsvaps; /* # wds mode vaps */
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uint8_t sc_nstavaps; /* # sta mode vaps */
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uint8_t sc_ndwdsvaps; /* # sta mode dwds vaps */
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uint8_t sc_nbssid0; /* # vap's using base mac */
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uint32_t sc_bssidmask; /* bssid mask */
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void (*sc_recv_mgmt)(struct ieee80211com *,
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struct mbuf *,
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struct ieee80211_node *,
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int, int, int, u_int32_t);
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int (*sc_newstate)(struct ieee80211com *,
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enum ieee80211_state, int);
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void (*sc_node_cleanup)(struct ieee80211_node *);
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void (*sc_node_drain)(struct ieee80211_node *);
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int (*sc_recv_action)(struct ieee80211_node *,
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const struct ieee80211_frame *,
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const uint8_t *, const uint8_t *);
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int (*sc_addba_request)(struct ieee80211_node *,
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struct ieee80211_tx_ampdu *,
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int dialogtoken, int baparamset,
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int batimeout);
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int (*sc_addba_response)(struct ieee80211_node *,
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struct ieee80211_tx_ampdu *,
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int status, int baparamset,
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int batimeout);
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void (*sc_addba_stop)(struct ieee80211_node *,
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struct ieee80211_tx_ampdu *);
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struct mwl_descdma sc_rxdma; /* rx bus dma resources */
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mwl_rxbufhead sc_rxbuf; /* rx buffers */
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struct mwl_rxbuf *sc_rxnext; /* next rx buffer to process */
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struct task sc_rxtask; /* rx int processing */
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void *sc_rxmem; /* rx dma buffer pool */
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bus_dma_tag_t sc_rxdmat; /* rx bus DMA tag */
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bus_size_t sc_rxmemsize; /* rx dma buffer pool size */
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bus_dmamap_t sc_rxmap; /* map for rx dma buffers */
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bus_addr_t sc_rxmem_paddr; /* physical addr of sc_rxmem */
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mwl_jumbohead sc_rxfree; /* list of free dma buffers */
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int sc_nrxfree; /* # buffers on rx free list */
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struct mtx sc_rxlock; /* lock on sc_rxfree */
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struct mwl_txq sc_txq[MWL_NUM_TX_QUEUES];
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struct mwl_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
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struct mbuf *sc_aggrq; /* aggregation q */
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struct task sc_txtask; /* tx int processing */
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struct task sc_bawatchdogtask;/* BA watchdog processing */
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struct task sc_radartask; /* radar detect processing */
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struct task sc_chanswitchtask;/* chan switch processing */
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uint8_t sc_staid[MWL_MAXSTAID/NBBY];
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int sc_ageinterval;
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struct callout sc_timer; /* periodic work */
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struct mwl_tx_radiotap_header sc_tx_th;
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struct mwl_rx_radiotap_header sc_rx_th;
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};
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#define MWL_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
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NULL, MTX_DEF | MTX_RECURSE)
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#define MWL_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define MWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define MWL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define MWL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define MWL_RXFREE_INIT(_sc) \
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mtx_init(&(_sc)->sc_rxlock, device_get_nameunit((_sc)->sc_dev), \
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NULL, MTX_DEF)
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#define MWL_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rxlock)
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#define MWL_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->sc_rxlock)
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#define MWL_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rxlock)
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#define MWL_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->sc_rxlock, MA_OWNED)
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int mwl_attach(u_int16_t, struct mwl_softc *);
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int mwl_detach(struct mwl_softc *);
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void mwl_resume(struct mwl_softc *);
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void mwl_suspend(struct mwl_softc *);
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void mwl_shutdown(void *);
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void mwl_intr(void *);
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#endif /* _DEV_MWL_MVVAR_H */
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