grehan 4900dd0aa5 Implement the 0x2B SUB instruction, and the OR variant of 0x81. ... Found with local APIC accesses from bitrig/amd64 bsd.rd, 07/15-snap. Reviewed by: neel MFC after: 3 days		2014-08-27 00:53:56 +00:00
..
acpica	don't set CR4 PSE bit on amd64	2014-07-23 15:53:29 +00:00
amd64	There exists a possible sequence of page table page allocation failures	2014-08-18 20:28:08 +00:00
conf	Fix build of si(4) and enable it in LINT on amd64 and i386.	2014-08-20 16:07:17 +00:00
ia32	x86: Allow users to change PSL_RF via ptrace(PT_SETREGS...)	2013-11-14 15:37:20 +00:00
include	Change __inline style to be consistent with FreeBSD usage,	2014-08-24 02:07:34 +00:00
linux32	Revert r266925 as it can lead to instant panic at fexecve():	2014-06-17 05:29:18 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	Implement the 0x2B SUB instruction, and the OR variant of 0x81.	2014-08-27 00:53:56 +00:00
Makefile