395e65aa29
should really be renamed to fpu.h and npx.c to fpu.c since its part of the core architecture on amd64 systems, not an isa 'numeric processor extension'.
114 lines
3.9 KiB
C
114 lines
3.9 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)npx.h 5.3 (Berkeley) 1/18/91
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* $FreeBSD$
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*/
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/*
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* 287/387 NPX Coprocessor Data Structures and Constants
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* W. Jolitz 1/90
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*/
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#ifndef _MACHINE_NPX_H_
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#define _MACHINE_NPX_H_
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/* Contents of each x87 floating point accumulator */
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struct fpacc87 {
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u_char fp_bytes[10];
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};
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/* Contents of each SSE extended accumulator */
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struct xmmacc {
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u_char xmm_bytes[16];
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};
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struct envxmm {
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u_int16_t en_cw; /* control word (16bits) */
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u_int16_t en_sw; /* status word (16bits) */
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u_int8_t en_tw; /* tag word (8bits) */
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u_int8_t en_zero;
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u_int16_t en_opcode; /* opcode last executed (11 bits ) */
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u_int64_t en_rip; /* floating point instruction pointer */
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u_int64_t en_rdp; /* floating operand pointer */
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u_int32_t en_mxcsr; /* SSE sontorol/status register */
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u_int32_t en_mxcsr_mask; /* valid bits in mxcsr */
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};
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struct savefpu {
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struct envxmm sv_env;
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struct {
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struct fpacc87 fp_acc;
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u_char fp_pad[6]; /* padding */
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} sv_fp[8];
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struct xmmacc sv_xmm[16];
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u_char sv_pad[96];
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} __aligned(16);
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/*
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* The hardware default control word for i387's and later coprocessors is
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* 0x37F, giving:
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*
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* We modify the affine mode bit and precision bits in this to give:
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*
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* affine mode for 287's (if they work at all) (1 in bitfield 1<<12)
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* 53-bit precision (2 in bitfield 3<<8)
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*
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* 64-bit precision often gives bad results with high level languages
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* because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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*/
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#define __INITIAL_NPXCW__ 0x127F
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#define __INITIAL_MXCSR__ 0x1F80
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#define __INITIAL_MXCSR_MASK__ 0xFFBF
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#ifdef _KERNEL
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int npxdna(void);
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void npxdrop(void);
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void npxexit(struct thread *td);
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int npxformat(void);
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int npxgetregs(struct thread *td, struct savefpu *addr);
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void npxinit(u_short control);
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void npxsave(struct savefpu *addr);
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void npxsetregs(struct thread *td, struct savefpu *addr);
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int npxtrap(void);
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#endif
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#endif /* !_MACHINE_NPX_H_ */
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