7fac2bd7e7
NetFPGA-10G Embedded CPU Ethernet Core. The current version operates on a simple PIO based interface connected to a NetFPGA-10G port. To avoid confusion: this driver operates on a CPU running on the FPGA, e.g. BERI/mips, and is not suited for the PCI host interface. MFC after: 1 week Relnotes: yes Sponsored by: DARPA/AFRL
37 lines
767 B
Plaintext
37 lines
767 B
Plaintext
#
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# BERI_NETFPGA_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
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# RISC Implementation) FPGA soft core, as configured in its NetFPGA reference
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# configuration.
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#
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# $FreeBSD$
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#
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include "BERI_TEMPLATE"
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ident BERI_NETFPGA_MDROOT
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options HZ=100
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options FDT
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=beri-netfpga.dts
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#device uart
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device altera_jtag_uart
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device bpf
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options DEVICE_POLLING
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device netfpga10g_nf10bmac
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#
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# This kernel configuration uses an embedded memory root file system.
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# Adjust the following path and size based on local requirements.
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#
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options MD_ROOT # MD is a potential root device
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options MD_ROOT_SIZE=26112 # 25.5MB
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options ROOTDEVNAME=\"ufs:md0\"
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#makeoptions MFS_IMAGE=/foo/baz/baz/mdroot.img
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# end
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