f8aaa684be
Modify MIPS page table entry (PTE) initialisation so that cachability bits are set only once, using is_cacheable_mem() to determine what caching properties are required, rather than also unconditionally setting PTE_C_CACHE in init_pte_prot(). As PTE_C_CACHE | PTE_C_UNCACHED == PTE_C_CACHE, this meant that all userspace memory mappings of device memory (incorrectly) used caching TLB entries. This is arguably not quite what we want, even though it is (more) consistent with the MIPS pmap design: PTE caching properties should be derived from machine-independent page table attributes, but this is a substantially more complex change as the MIPS pmap doesn't yet know about page attributes, causing it to ignore requests by device drivers that want uncached userspace memory mappings as they describe memory-mapped FIFOs or shared memory with a device not participating in the cache coherence scheme. This fixes cacheability issues (specifically, undesired and unrequested caching) seen in userspace memory mappings of Avalon SoC bus device memory on BERI MIPS. Discussed with: jmallett, alc Sponsored by: DARPA, AFRL MFC after: 3 days |
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| adm5120 | ||
| alchemy | ||
| atheros | ||
| cavium | ||
| compile | ||
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| gxemul | ||
| idt | ||
| include | ||
| malta | ||
| mips | ||
| nlm | ||
| rmi | ||
| rt305x | ||
| sentry5 | ||
| sibyte | ||