mmel a0d10caff7 EHCI: Make core reset and port speed reading more generic. ... Use driver settable callbacks for handling of: - core post reset - reading actual port speed Typically, OTG enabled EHCI cores wants setting of USBMODE register, but this register is not defined in EHCI specification and different cores can have it on different offset. Also, for cores with TT extension, actual port speed must be determinable. But again, EHCI specification not covers this so this patch provides function for two most common variant of speed bits layout. Reviewed by: hselasky Differential Revision: https://reviews.freebsd.org/D5088		2016-01-28 14:11:59 +00:00
..
imx	Quick exit after setting the clock control register.	2016-01-17 23:03:21 +00:00
vybrid	EHCI: Make core reset and port speed reading more generic.	2016-01-28 14:11:59 +00:00
fsl_ocotp.c	The ocotp driver provides access to registers containing chip configuration	2014-09-02 02:54:55 +00:00
fsl_ocotpreg.h	Make it possible to access the ocotp registers before the ocotp device	2014-02-16 03:09:39 +00:00
fsl_ocotpvar.h	It turns out Freescale cleverly made the ocotp device compatible across	2014-02-15 21:21:57 +00:00