649b177fe3
Make it clearer what each one means in the comments that define them. IIC_BUSBSY was used in many places to mean two different things, either "someone else has reserved the bus so you have to wait until they're done" or "the signal level on the bus was not in the state I expected before/after issuing some command". Now IIC_BUSERR is used consistantly to refer to protocol/signaling errors, and IIC_BUSBSY refers to ownership/reservation of the bus.
483 lines
14 KiB
C
483 lines
14 KiB
C
/*-
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* Copyright (C) 2008-2009 Semihalf, Michal Hajduk
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org>
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* All rights reserved.
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*
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* Portions of this software were developed by Oleksandr Rybalko
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* I2C driver for Freescale i.MX hardware.
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*
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* Note that the hardware is capable of running as both a master and a slave.
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* This driver currently implements only master-mode operations.
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*
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* This driver supports multi-master i2c busses, by detecting bus arbitration
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* loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of
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* retries if some other master jumps onto the bus and interrupts one of our
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* transfer cycles resulting in arbitration loss in mid-transfer. The caller
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* must handle retries in a way that makes sense for the slave being addressed.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define I2C_ADDR_REG 0x00 /* I2C slave address register */
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#define I2C_FDR_REG 0x04 /* I2C frequency divider register */
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#define I2C_CONTROL_REG 0x08 /* I2C control register */
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#define I2C_STATUS_REG 0x0C /* I2C status register */
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#define I2C_DATA_REG 0x10 /* I2C data register */
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#define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */
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#define I2CCR_MEN (1 << 7) /* Module enable */
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#define I2CCR_MSTA (1 << 5) /* Master/slave mode */
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#define I2CCR_MTX (1 << 4) /* Transmit/receive mode */
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#define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */
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#define I2CCR_RSTA (1 << 2) /* Repeated START */
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#define I2CSR_MCF (1 << 7) /* Data transfer */
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#define I2CSR_MASS (1 << 6) /* Addressed as a slave */
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#define I2CSR_MBB (1 << 5) /* Bus busy */
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#define I2CSR_MAL (1 << 4) /* Arbitration lost */
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#define I2CSR_SRW (1 << 2) /* Slave read/write */
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#define I2CSR_MIF (1 << 1) /* Module interrupt */
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#define I2CSR_RXAK (1 << 0) /* Received acknowledge */
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#define I2C_BAUD_RATE_FAST 0x31
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#define I2C_BAUD_RATE_DEF 0x3F
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#define I2C_DFSSR_DIV 0x10
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/*
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* A table of available divisors and the associated coded values to put in the
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* FDR register to achieve that divisor.. There is no algorithmic relationship I
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* can see between divisors and the codes that go into the register. The table
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* begins and ends with entries that handle insane configuration values.
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*/
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struct clkdiv {
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u_int divisor;
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u_int regcode;
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};
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static struct clkdiv clkdiv_table[] = {
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{ 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 },
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{ 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 },
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{ 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 },
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{ 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a },
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{ 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d },
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{ 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c },
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{ 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f },
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{ 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 },
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{ 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 },
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{ 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 },
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{ 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d },
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{ 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c },
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{ 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f}
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};
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6q-i2c", 1},
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{"fsl,imx-i2c", 1},
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{NULL, 0}
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};
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struct i2c_softc {
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device_t dev;
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device_t iicbus;
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struct resource *res;
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int rid;
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sbintime_t byte_time_sbt;
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};
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static phandle_t i2c_get_node(device_t, device_t);
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static int i2c_probe(device_t);
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static int i2c_attach(device_t);
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static int i2c_repeated_start(device_t, u_char, int);
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static int i2c_start(device_t, u_char, int);
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static int i2c_stop(device_t);
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static int i2c_reset(device_t, u_char, u_char, u_char *);
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static int i2c_read(device_t, char *, int, int *, int, int);
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static int i2c_write(device_t, const char *, int, int *, int);
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static device_method_t i2c_methods[] = {
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DEVMETHOD(device_probe, i2c_probe),
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DEVMETHOD(device_attach, i2c_attach),
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/* OFW methods */
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DEVMETHOD(ofw_bus_get_node, i2c_get_node),
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DEVMETHOD(iicbus_callback, iicbus_null_callback),
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DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
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DEVMETHOD(iicbus_start, i2c_start),
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DEVMETHOD(iicbus_stop, i2c_stop),
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DEVMETHOD(iicbus_reset, i2c_reset),
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DEVMETHOD(iicbus_read, i2c_read),
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DEVMETHOD(iicbus_write, i2c_write),
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DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
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DEVMETHOD_END
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};
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static driver_t i2c_driver = {
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"iichb",
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i2c_methods,
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sizeof(struct i2c_softc),
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};
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static devclass_t i2c_devclass;
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DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
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DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
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static phandle_t
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i2c_get_node(device_t bus, device_t dev)
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{
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/*
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* Share controller node with iicbus device
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*/
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return ofw_bus_get_node(bus);
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}
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static __inline void
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i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val)
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{
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bus_write_1(sc->res, off, val);
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}
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static __inline uint8_t
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i2c_read_reg(struct i2c_softc *sc, bus_size_t off)
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{
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return (bus_read_1(sc->res, off));
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}
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static __inline void
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i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask)
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{
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uint8_t status;
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status = i2c_read_reg(sc, off);
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status |= mask;
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i2c_write_reg(sc, off, status);
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}
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/* Wait for bus to become busy or not-busy. */
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static int
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wait_for_busbusy(struct i2c_softc *sc, int wantbusy)
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{
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int retry, srb;
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retry = 1000;
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while (retry --) {
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srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB;
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if ((srb && wantbusy) || (!srb && !wantbusy))
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return (IIC_NOERR);
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DELAY(1);
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}
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return (IIC_ETIMEOUT);
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}
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/* Wait for transfer to complete, optionally check RXAK. */
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static int
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wait_for_xfer(struct i2c_softc *sc, int checkack)
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{
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int retry, sr;
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/*
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* Sleep for about the time it takes to transfer a byte (with precision
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* set to tolerate 5% oversleep). We calculate the approximate byte
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* transfer time when we set the bus speed divisor. Slaves are allowed
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* to do clock-stretching so the actual transfer time can be larger, but
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* this gets the bulk of the waiting out of the way without tying up the
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* processor the whole time.
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*/
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pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0);
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retry = 10000;
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while (retry --) {
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sr = i2c_read_reg(sc, I2C_STATUS_REG);
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if (sr & I2CSR_MIF) {
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if (sr & I2CSR_MAL)
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return (IIC_EBUSERR);
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else if (checkack && (sr & I2CSR_RXAK))
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return (IIC_ENOACK);
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else
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return (IIC_NOERR);
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}
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DELAY(1);
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}
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return (IIC_ETIMEOUT);
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}
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/*
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* Implement the error handling shown in the state diagram of the imx6 reference
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* manual. If there was an error, then:
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* - Clear master mode (MSTA and MTX).
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* - Wait for the bus to become free or for a timeout to happen.
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* - Disable the controller.
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*/
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static int
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i2c_error_handler(struct i2c_softc *sc, int error)
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{
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if (error != 0) {
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i2c_write_reg(sc, I2C_STATUS_REG, 0);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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wait_for_busbusy(sc, false);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0);
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}
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return (error);
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}
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static int
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i2c_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Freescale i.MX I2C");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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i2c_attach(device_t dev)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->rid = 0;
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
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RF_ACTIVE);
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if (sc->res == NULL) {
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device_printf(dev, "could not allocate resources");
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return (ENXIO);
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}
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "could not add iicbus child");
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return (ENXIO);
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}
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bus_generic_attach(dev);
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return (0);
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}
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static int
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i2c_repeated_start(device_t dev, u_char slave, int timeout)
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{
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struct i2c_softc *sc;
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int error;
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sc = device_get_softc(dev);
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if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) {
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return (IIC_EBUSERR);
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}
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/*
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* Set repeated start condition, delay (per reference manual, min 156nS)
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* before writing slave address, wait for ack after write.
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*/
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i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA);
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DELAY(1);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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i2c_write_reg(sc, I2C_DATA_REG, slave);
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error = wait_for_xfer(sc, true);
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return (i2c_error_handler(sc, error));
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}
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static int
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i2c_start(device_t dev, u_char slave, int timeout)
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{
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struct i2c_softc *sc;
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int error;
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sc = device_get_softc(dev);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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DELAY(10); /* Delay for controller to sample bus state. */
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if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) {
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return (i2c_error_handler(sc, IIC_EBUSERR));
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}
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX);
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if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR)
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return (i2c_error_handler(sc, error));
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i2c_write_reg(sc, I2C_STATUS_REG, 0);
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i2c_write_reg(sc, I2C_DATA_REG, slave);
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error = wait_for_xfer(sc, true);
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return (i2c_error_handler(sc, error));
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}
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static int
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i2c_stop(device_t dev)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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wait_for_busbusy(sc, false);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0);
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return (IIC_NOERR);
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}
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static int
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i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
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{
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struct i2c_softc *sc;
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u_int busfreq, div, i, ipgfreq;
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sc = device_get_softc(dev);
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/*
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* Look up the divisor that gives the nearest speed that doesn't exceed
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* the configured value for the bus.
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*/
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ipgfreq = imx_ccm_ipg_hz();
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busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
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div = (ipgfreq + busfreq - 1) / busfreq;
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for (i = 0; i < nitems(clkdiv_table); i++) {
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if (clkdiv_table[i].divisor >= div)
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break;
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}
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/*
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* Calculate roughly how long it will take to transfer a byte (which
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* requires 9 clock cycles) at the new bus speed. This value is used to
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* pause() while waiting for transfer-complete. With a 66MHz IPG clock
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* and the actual i2c bus speeds that leads to, for nominal 100KHz and
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* 400KHz bus speeds the transfer times are roughly 104uS and 22uS.
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*/
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busfreq = ipgfreq / clkdiv_table[i].divisor;
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sc->byte_time_sbt = SBT_1US * (9000000 / busfreq);
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/*
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* Disable the controller (do the reset), and set the new clock divisor.
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*/
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
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i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode);
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return (IIC_NOERR);
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}
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static int
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i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
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{
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struct i2c_softc *sc;
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int error, reg;
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sc = device_get_softc(dev);
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*read = 0;
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if (len) {
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if (len == 1)
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
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I2CCR_MSTA | I2CCR_TXAK);
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else
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
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I2CCR_MSTA);
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/* Dummy read to prime the receiver. */
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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i2c_read_reg(sc, I2C_DATA_REG);
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}
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error = 0;
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*read = 0;
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while (*read < len) {
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if ((error = wait_for_xfer(sc, false)) != IIC_NOERR)
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break;
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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if (last) {
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if (*read == len - 2) {
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/* NO ACK on last byte */
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
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I2CCR_MSTA | I2CCR_TXAK);
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} else if (*read == len - 1) {
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|
/* Transfer done, signal stop. */
|
|
i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
|
|
I2CCR_TXAK);
|
|
wait_for_busbusy(sc, false);
|
|
}
|
|
}
|
|
reg = i2c_read_reg(sc, I2C_DATA_REG);
|
|
*buf++ = reg;
|
|
(*read)++;
|
|
}
|
|
|
|
return (i2c_error_handler(sc, error));
|
|
}
|
|
|
|
static int
|
|
i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
|
|
{
|
|
struct i2c_softc *sc;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
error = 0;
|
|
*sent = 0;
|
|
while (*sent < len) {
|
|
i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
|
|
i2c_write_reg(sc, I2C_DATA_REG, *buf++);
|
|
if ((error = wait_for_xfer(sc, true)) != IIC_NOERR)
|
|
break;
|
|
(*sent)++;
|
|
}
|
|
|
|
return (i2c_error_handler(sc, error));
|
|
}
|