1abcdbd127
CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
246 lines
10 KiB
C
246 lines
10 KiB
C
/*-
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* Copyright (c) 2006 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*-
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* Copyright (c) 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef ARM_XSCALE_IXP425_QMGR_H
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#define ARM_XSCALE_IXP425_QMGR_H
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#define IX_QMGR_MAX_NUM_QUEUES 64
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#define IX_QMGR_MIN_QUEUPP_QID 32
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#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
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/* Total size of SRAM */
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#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
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#define IX_QMGR_Q_PRIORITY_0 0
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#define IX_QMGR_Q_PRIORITY_1 1
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#define IX_QMGR_Q_PRIORITY_2 2
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#define IX_QMGR_NUM_PRIORITY_LEVELS 3 /* number of priority levels */
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#define IX_QMGR_Q_STATUS_E_BIT_MASK 0x1 /* Empty */
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#define IX_QMGR_Q_STATUS_NE_BIT_MASK 0x2 /* Nearly Empty */
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#define IX_QMGR_Q_STATUS_NF_BIT_MASK 0x4 /* Nearly Full */
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#define IX_QMGR_Q_STATUS_F_BIT_MASK 0x8 /* Full */
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#define IX_QMGR_Q_STATUS_UF_BIT_MASK 0x10 /* Underflow */
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#define IX_QMGR_Q_STATUS_OF_BIT_MASK 0x20 /* Overflow */
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#define IX_QMGR_Q_SOURCE_ID_E 0 /* Q Empty after last read */
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#define IX_QMGR_Q_SOURCE_ID_NE 1 /* Q Nearly Empty after last read */
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#define IX_QMGR_Q_SOURCE_ID_NF 2 /* Q Nearly Full after last write */
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#define IX_QMGR_Q_SOURCE_ID_F 3 /* Q Full after last write */
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#define IX_QMGR_Q_SOURCE_ID_NOT_E 4 /* Q !Empty after last write */
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#define IX_QMGR_Q_SOURCE_ID_NOT_NE 5 /* Q !Nearly Empty after last write */
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#define IX_QMGR_Q_SOURCE_ID_NOT_NF 6 /* Q !Nearly Full after last read */
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#define IX_QMGR_Q_SOURCE_ID_NOT_F 7 /* Q !Full after last read */
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#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0 /* underflow bit mask */
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#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1 /* overflow bit mask */
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#define IX_QMGR_QUEACC0_OFFSET 0x0000 /* q 0 access register */
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#define IX_QMGR_QUEACC_SIZE 0x4/*words*/
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#define IX_QMGR_QUELOWSTAT0_OFFSET 0x400 /* Q status, q's 0-7 */
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#define IX_QMGR_QUELOWSTAT1_OFFSET 0x404 /* Q status, q's 8-15 */
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#define IX_QMGR_QUELOWSTAT2_OFFSET 0x408 /* Q status, q's 16-23 */
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#define IX_QMGR_QUELOWSTAT3_OFFSET 0x40c /* Q status, q's 24-31 */
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/* Queue status register Q status bits mask */
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#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
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/* Size of queue 0-31 status register */
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#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
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#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 8 /* # status/word */
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#define IX_QMGR_QUEUOSTAT0_OFFSET 0x410 /* Q UF/OF status, q's 0-15 */
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#define IX_QMGR_QUEUOSTAT1_OFFSET 0x414 /* Q UF/OF status, q's 16-31 */
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#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 16 /* # UF/OF status/word */
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#define IX_QMGR_QUEUPPSTAT0_OFFSET 0x418 /* NE status, q's 32-63 */
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#define IX_QMGR_QUEUPPSTAT1_OFFSET 0x41c /* F status, q's 32-63 */
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#define IX_QMGR_INT0SRCSELREG0_OFFSET 0x420 /* INT src select, q's 0-7 */
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#define IX_QMGR_INT0SRCSELREG1_OFFSET 0x424 /* INT src select, q's 8-15 */
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#define IX_QMGR_INT0SRCSELREG2_OFFSET 0x428 /* INT src select, q's 16-23 */
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#define IX_QMGR_INT0SRCSELREG3_OFFSET 0x42c /* INT src select, q's 24-31 */
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#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 8 /* # INT src select/word */
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#define IX_QMGR_QUEIEREG0_OFFSET 0x430 /* INT enable, q's 0-31 */
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#define IX_QMGR_QUEIEREG1_OFFSET 0x434 /* INT enable, q's 32-63 */
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#define IX_QMGR_QINTREG0_OFFSET 0x438 /* INT status, q's 0-31 */
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#define IX_QMGR_QINTREG1_OFFSET 0x43c /* INT status, q's 32-63 */
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#define IX_QMGR_QUECONFIG_BASE_OFFSET 0x2000 /* Q config register, q 0 */
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#define IX_QMGR_QUECONFIG_SIZE 0x100 /* total size of Q config regs*/
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#define IX_QMGR_QUEBUFFER_SPACE_OFFSET 0x2100 /* start of SRAM */
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/* Total bits in a word */
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#define BITS_PER_WORD 32
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/* Size of queue buffer space */
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#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
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/*
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* This macro will return the address of the access register for the
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* queue specified by qId
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*/
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#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
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(((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\
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+ IX_QMGR_QUEACC0_OFFSET)
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/*
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* Bit location of bit-3 of INT0SRCSELREG0 register to enabled
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* sticky interrupt register.
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*/
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#define IX_QMGR_INT0SRCSELREG0_BIT3 3
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/*
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* These defines are the bit offsets of the various fields of
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* the queue configuration register.
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*/
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#if 0
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#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00
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#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07
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#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E
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#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16
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#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18
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#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A
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#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D
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#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF
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#define IX_QMGR_NE_MASK 0x7
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#define IX_QMGR_NF_MASK 0x7
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#define IX_QMGR_SIZE_MASK 0x3
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#define IX_QMGR_ENTRY_SIZE_MASK 0x3
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#define IX_QMGR_BADDR_MASK 0x003FC000
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#define IX_QMGR_RDPTR_MASK 0x7F
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#define IX_QMGR_WRPTR_MASK 0x7F
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#define IX_QMGR_RDWRPTR_MASK 0x00003FFF
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#else
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#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0
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#define IX_QMGR_WRPTR_MASK 0x7F
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#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 7
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#define IX_QMGR_RDPTR_MASK 0x7F
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#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 14
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#define IX_QMGR_BADDR_MASK 0x3FC000 /* XXX not used */
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#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 22
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#define IX_QMGR_ENTRY_SIZE_MASK 0x3
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#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 24
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#define IX_QMGR_SIZE_MASK 0x3
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#define IX_QMGR_Q_CONFIG_NE_OFFSET 26
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#define IX_QMGR_NE_MASK 0x7
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#define IX_QMGR_Q_CONFIG_NF_OFFSET 29
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#define IX_QMGR_NF_MASK 0x7
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#define IX_QMGR_RDWRPTR_MASK 0x00003FFF
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#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF
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#endif
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#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 64
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#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 6
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#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
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/* Base address of AQM SRAM */
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#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
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((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
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/* Min buffer size used for generating buffer size in QUECONFIG */
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#define IX_QMGR_MIN_BUFFER_SIZE 16
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/* Reset values of QMgr hardware registers */
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#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333
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#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000
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#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF
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#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000
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#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
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#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000
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#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF
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#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000
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#define IX_QMGR_QUELOWSTAT_BITS_PER_Q \
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(BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
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#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
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#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
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(((qId) * sizeof(uint32_t)) + IX_QMGR_QUECONFIG_BASE_OFFSET)
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#define IX_QMGR_ENTRY1_OFFSET 0
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#define IX_QMGR_ENTRY2_OFFSET 1
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#define IX_QMGR_ENTRY4_OFFSET 3
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typedef void qconfig_hand_t(int, void *);
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int ixpqmgr_qconfig(int qId, int qSizeInWords, int ne, int nf, int srcSel,
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qconfig_hand_t *cb, void *cbarg);
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int ixpqmgr_qwrite(int qId, uint32_t entry);
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int ixpqmgr_qread(int qId, uint32_t *entry);
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int ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p);
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uint32_t ixpqmgr_getqstatus(int qId);
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uint32_t ixpqmgr_getqconfig(int qId);
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void ixpqmgr_notify_enable(int qId, int srcSel);
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void ixpqmgr_notify_disable(int qId);
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void ixpqmgr_dump(void);
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#endif /* ARM_XSCALE_IXP425_QMGR_H */
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