1b9328de56
Here, "suitably endowed" means that the System Control Coprocessor (#15) has Performance Monitoring Registers, including a CCNT (Cycle Count) register. The CCNT register is used in a way similar to the TSC register in x86 processors by the get_cyclecount(9) function. The entropy-harvesting thread is a heavy user of this function, and will benefit from not having to call binuptime(9) instead. One problem with the CCNT register is that it is 32-bit only, so the upper 32-bits of the returned number are always 0. The entropy harvester does not care, but in case any one else does, follow-up work may include an interrup trap to increment an upper-32-bit counter on CCNT overflow. Another problem is that the CCNT register is not readable in user-mode code; in can be made readable by userland, but then it is also writable, and so is a good chunk of the PMU system. For that reason, the CCNT is not enabled for user-mode access in this commit. Like the x86, there is one CCNT per core, so they don't all run in perfect sync. Reviewed by: ian@ (an earlier version) Tested by: ian@ (same earlier version) Committed from: WANDBOARD-QUAD
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */
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/* $FreeBSD$ */
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#ifndef MACHINE_CPU_H
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#define MACHINE_CPU_H
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#include <machine/armreg.h>
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#include <machine/frame.h>
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void cpu_halt(void);
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void swi_vm(void *);
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#ifdef _KERNEL
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static __inline uint64_t
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get_cyclecount(void)
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{
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/* This '#if' asks the question 'Does CP15/SCC include performance counters?' */
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
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|| defined(CPU_MV_PJ4B) \
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|| defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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uint32_t ccnt;
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uint64_t ccnt64;
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/*
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* Read PMCCNTR. Curses! Its only 32 bits.
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* TODO: Fix this by catching overflow with interrupt?
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*/
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__asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
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ccnt64 = (uint64_t)ccnt;
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return (ccnt64);
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#else /* No performance counters, so use binuptime(9). This is slooooow */
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struct bintime bt;
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binuptime(&bt);
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return ((uint64_t)bt.sec << 56 | bt.frac >> 8);
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#endif
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}
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#endif
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#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
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#define TRAPF_PC(tfp) ((tfp)->tf_pc)
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#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp)
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#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp))
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#define cpu_spinwait() /* nothing */
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#define ARM_NVEC 8
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#define ARM_VEC_ALL 0xffffffff
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extern vm_offset_t vector_page;
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/*
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* Params passed into initarm. If you change the size of this you will
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* need to update locore.S to allocate more memory on the stack before
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* it calls initarm.
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*/
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struct arm_boot_params {
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register_t abp_size; /* Size of this structure */
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register_t abp_r0; /* r0 from the boot loader */
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register_t abp_r1; /* r1 from the boot loader */
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register_t abp_r2; /* r2 from the boot loader */
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register_t abp_r3; /* r3 from the boot loader */
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vm_offset_t abp_physaddr; /* The kernel physical address */
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vm_offset_t abp_pagetable; /* The early page table */
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};
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void arm_vector_init(vm_offset_t, int);
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void fork_trampoline(void);
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void identify_arm_cpu(void);
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void *initarm(struct arm_boot_params *);
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extern char btext[];
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extern char etext[];
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int badaddr_read(void *, size_t, void *);
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#endif /* !MACHINE_CPU_H */
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