Originally, I overlooked that PMIO register 0xc0 has a dual personality.
It can either be S5/Reset Status register or Misc. Fix register (aka
debug status register). The mode is controlled by bit 2 in PMIO
register 0xc4. Apparently there are register programming requirements
for the second personality, so many BIOSes leave the register, after
programming it, in that mode. So, we need to switch the register to the
correct mode.
Additionally, AMDSB8_WD_RST_STS was defined incorrectly as bit 13 while
it is actually bit 25 (and the register's width is 32 bits, not 16).
With this change I see the following in dmesg after a reset by the
watchdog:
amdsbwd0: ResetStatus = 0x42000000
amdsbwd0: Previous Reset was caused by Watchdog
MFC after: 2 weeks
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