565 lines
16 KiB
C
565 lines
16 KiB
C
/*
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* Low level routines for Second Generation
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* Advanced Systems Inc. SCSI controllers chips
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*
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* Copyright (c) 1998 Justin Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Ported from:
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* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
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*
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* Copyright (c) 1995-1998 Advanced System Products, Inc.
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* All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that redistributions of source
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* code retain the above copyright notice and this comment without
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* modification.
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*/
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/bus_pio.h>
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#include <machine/bus_memio.h>
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#include <machine/bus.h>
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#include <machine/clock.h>
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#include <cam/cam.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/advansys/adwlib.h>
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struct adw_eeprom adw_default_eeprom = {
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ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
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0x0000, /* cfg_msw */
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0xFFFF, /* disc_enable */
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0xFFFF, /* wdtr_able */
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0xFFFF, /* sdtr_able */
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0xFFFF, /* start_motor */
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0xFFFF, /* tagqng_able */
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0xFFFF, /* bios_scan */
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0, /* scam_tolerant */
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7, /* adapter_scsi_id */
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0, /* bios_boot_delay */
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3, /* scsi_reset_delay */
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0, /* bios_id_lun */
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0, /* termination */
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0, /* reserved1 */
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{ /* Bios Ctrl */
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1, 1, 1, 1, 1,
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1, 1, 1, 1, 1,
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},
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0xFFFF, /* ultra_able */
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0, /* reserved2 */
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ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
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ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
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0, /* dvc_cntl */
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0, /* bug_fix */
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{ 0, 0, 0 }, /* serial_number */
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0, /* check_sum */
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{ /* oem_name[16] */
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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},
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0, /* dvc_err_code */
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0, /* adv_err_code */
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0, /* adv_err_addr */
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0, /* saved_dvc_err_code */
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0, /* saved_adv_err_code */
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0, /* saved_adv_err_addr */
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0 /* num_of_err */
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};
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static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
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static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
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u_int data);
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static void adw_eeprom_wait(struct adw_softc *adw);
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int
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adw_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh)
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{
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if (bus_space_read_1(tag, bsh, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
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&& bus_space_read_2(tag, bsh, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
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return (1);
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return (0);
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}
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/*
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* Reset Chip.
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*/
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void
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adw_reset_chip(struct adw_softc *adw)
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{
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adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
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DELAY(100);
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adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
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/*
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* Initialize Chip registers.
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*/
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adw_outb(adw, ADW_MEM_CFG,
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adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
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adw_outw(adw, ADW_SCSI_CFG1,
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adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
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/*
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* Setting the START_CTL_EM_FU 3:2 bits sets a FIFO threshold
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* of 128 bytes. This register is only accessible to the host.
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*/
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adw_outb(adw, ADW_DMA_CFG0,
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ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
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}
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/*
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* Read the specified EEPROM location
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*/
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static u_int16_t
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adw_eeprom_read_16(struct adw_softc *adw, int addr)
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{
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adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
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adw_eeprom_wait(adw);
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return (adw_inw(adw, ADW_EEP_DATA));
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}
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static void
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adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
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{
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adw_outw(adw, ADW_EEP_DATA, data);
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adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
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adw_eeprom_wait(adw);
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}
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/*
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* Wait for and EEPROM command to complete
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*/
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static void
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adw_eeprom_wait(struct adw_softc *adw)
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{
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int i;
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for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
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if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
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break;
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DELAY(1000);
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}
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if (i == ADW_EEP_DELAY_MS)
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panic("%s: Timedout Reading EEPROM", adw_name(adw));
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}
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/*
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* Read EEPROM configuration into the specified buffer.
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*
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* Return a checksum based on the EEPROM configuration read.
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*/
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u_int16_t
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adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
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{
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u_int16_t *wbuf;
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u_int16_t wval;
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u_int16_t chksum;
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int eep_addr;
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wbuf = (u_int16_t *)eep_buf;
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chksum = 0;
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for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
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eep_addr < ADW_EEP_DVC_CFG_END;
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eep_addr++, wbuf++) {
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wval = adw_eeprom_read_16(adw, eep_addr);
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chksum += wval;
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*wbuf = wval;
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}
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/* checksum field is not counted in the checksum */
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*wbuf = adw_eeprom_read_16(adw, eep_addr);
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wbuf++;
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/* Driver seeprom variables are not included in the checksum */
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for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
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eep_addr < ADW_EEP_MAX_WORD_ADDR;
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eep_addr++, wbuf++)
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*wbuf = adw_eeprom_read_16(adw, eep_addr);
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return (chksum);
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}
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void
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adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
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{
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u_int16_t *wbuf;
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u_int16_t addr;
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u_int16_t chksum;
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wbuf = (u_int16_t *)eep_buf;
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chksum = 0;
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adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
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adw_eeprom_wait(adw);
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/*
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* Write EEPROM until checksum.
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*/
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for (addr = ADW_EEP_DVC_CFG_BEGIN;
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addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
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chksum += *wbuf;
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adw_eeprom_write_16(adw, addr, *wbuf);
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}
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/*
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* Write calculated EEPROM checksum
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*/
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adw_eeprom_write_16(adw, addr, chksum);
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/* skip over buffer's checksum */
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wbuf++;
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/*
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* Write the rest.
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*/
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for (addr = ADW_EEP_DVC_CTL_BEGIN;
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addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
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adw_eeprom_write_16(adw, addr, *wbuf);
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adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
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adw_eeprom_wait(adw);
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}
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int
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adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
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{
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u_int8_t biosmem[ADW_MC_BIOSLEN];
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u_int16_t *mcodebuf;
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u_int addr;
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u_int end_addr;
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u_int checksum;
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u_int scsicfg1;
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u_int i;
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/*
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* Save the RISC memory BIOS region before writing the microcode.
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* The BIOS may already be loaded and using its RISC LRAM region
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* so its region must be saved and restored.
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*/
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for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
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biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
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/*
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* Load the Microcode. Casting here was less work than
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* reformatting the supplied microcode into an array of
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* 16bit values...
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*/
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mcodebuf = (u_int16_t *)adw_mcode;
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adw_outw(adw, ADW_RAM_ADDR, 0);
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for (addr = 0; addr < adw_mcode_size/2; addr++)
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adw_outw(adw, ADW_RAM_DATA, mcodebuf[addr]);
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/*
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* Clear the rest of LRAM.
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*/
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for (; addr < ADW_CONDOR_MEMSIZE/2; addr++)
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adw_outw(adw, ADW_RAM_DATA, 0);
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/*
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* Verify the microcode checksum.
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*/
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checksum = 0;
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adw_outw(adw, ADW_RAM_ADDR, 0);
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for (addr = 0; addr < adw_mcode_size/2; addr++)
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checksum += adw_inw(adw, ADW_RAM_DATA);
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if (checksum != adw_mcode_chksum) {
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printf("%s: Firmware load failed!\n", adw_name(adw));
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return (-1);
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}
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/*
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* Restore the RISC memory BIOS region.
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*/
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for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
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adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
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/*
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* Calculate and write the microcode code checksum to
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* the microcode code checksum location.
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*/
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addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR) / 2;
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end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR) / 2;
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checksum = 0;
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for (; addr < end_addr; addr++)
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checksum += mcodebuf[addr];
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adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
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/*
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* Initialize microcode operating variables
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*/
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adw_lram_write_16(adw, ADW_MC_ADAPTER_SCSI_ID, adw->initiator_id);
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/*
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* Leave WDTR and SDTR negotiation disabled until the XPT has
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* informed us of device capabilities, but do set the ultra mask
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* in case we receive an SDTR request from the target before we
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* negotiate. We turn on tagged queuing at the microcode level
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* for all devices, and modulate this on a per command basis.
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*/
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adw_lram_write_16(adw, ADW_MC_ULTRA_ABLE, adw->user_ultra);
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adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
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adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
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/*
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* Set SCSI_CFG0 Microcode Default Value.
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*
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* The microcode will set the SCSI_CFG0 register using this value
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* after it is started.
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*/
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adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
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ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
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ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
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/*
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* Determine SCSI_CFG1 Microcode Default Value.
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*
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* The microcode will set the SCSI_CFG1 register using this value
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* after it is started below.
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*/
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scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
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/*
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* If all three connectors are in use, return an error.
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*/
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if ((scsicfg1 & ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK) == 0
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|| (scsicfg1 & ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK) == 0) {
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printf("%s: Illegal Cable Config!\n", adw_name(adw));
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printf("%s: Only Two Ports may be used at a time!\n",
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adw_name(adw));
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return (-1);
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}
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/*
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* If the internal narrow cable is reversed all of the SCSI_CTRL
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* register signals will be set. Check for and return an error if
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* this condition is found.
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*/
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if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
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printf("%s: Illegal Cable Config!\n", adw_name(adw));
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printf("%s: Internal cable is reversed!\n", adw_name(adw));
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return (-1);
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}
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/*
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* If this is a differential board and a single-ended device
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* is attached to one of the connectors, return an error.
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*/
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if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
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&& (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
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printf("%s: A Single Ended Device is attached to our "
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"differential bus!\n", adw_name(adw));
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return (-1);
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}
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/*
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* Perform automatic termination control if desired.
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*/
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if (term_scsicfg1 == 0) {
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switch(scsicfg1 & ADW_SCSI_CFG1_CABLE_DETECT) {
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case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_INT8_MASK):
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case (ADW_SCSI_CFG1_INT16_MASK|
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ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT8_MASK):
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case (ADW_SCSI_CFG1_INT16_MASK|
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ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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case (ADW_SCSI_CFG1_INT16_MASK|
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ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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case (ADW_SCSI_CFG1_INT8_MASK|
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ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_INT8_MASK|
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ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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/* Two out of three cables missing. Both on. */
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term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L
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| ADW_SCSI_CFG1_TERM_CTL_H;
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break;
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case (ADW_SCSI_CFG1_INT16_MASK):
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case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_EXT8_MASK):
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case (ADW_SCSI_CFG1_INT16_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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case (ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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case (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_EXT16_MASK):
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/* No two 16bit cables present. High on. */
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term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
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break;
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case (ADW_SCSI_CFG1_INT8_MASK):
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case (ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_EXT8_MASK):
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/* Wide -> Wide or Narrow -> Wide. Both off */
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break;
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}
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}
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/* Tell the user about our decission */
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switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
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case ADW_SCSI_CFG1_TERM_CTL_MASK:
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printf("High & Low Termination Enabled, ");
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break;
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case ADW_SCSI_CFG1_TERM_CTL_H:
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printf("High Termination Enabled, ");
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break;
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case ADW_SCSI_CFG1_TERM_CTL_L:
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printf("Low Termination Enabled, ");
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break;
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default:
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break;
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}
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/*
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* Invert the TERM_CTL_H and TERM_CTL_L bits and then
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* set 'scsicfg1'. The TERM_POL bit does not need to be
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* referenced, because the hardware internally inverts
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* the Termination High and Low bits if TERM_POL is set.
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*/
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term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
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scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
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scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
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/*
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* Set SCSI_CFG1 Microcode Default Value
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*
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* Set filter value and possibly modified termination control
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* bits in the Microcode SCSI_CFG1 Register Value.
|
|
*
|
|
* The microcode will set the SCSI_CFG1 register using this value
|
|
* after it is started below.
|
|
*/
|
|
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1,
|
|
scsicfg1 | ADW_SCSI_CFG1_FLTR_11_TO_20NS);
|
|
|
|
/*
|
|
* Only accept selections on our initiator target id.
|
|
* This may change in target mode scenarios...
|
|
*/
|
|
adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
|
|
(0x01 << adw->initiator_id));
|
|
|
|
/*
|
|
* Link all the RISC Queue Lists together in a doubly-linked
|
|
* NULL terminated list.
|
|
*
|
|
* Skip the NULL (0) queue which is not used.
|
|
*/
|
|
for (i = 1, addr = ADW_MC_RISC_Q_LIST_BASE + ADW_MC_RISC_Q_LIST_SIZE;
|
|
i < ADW_MC_RISC_Q_TOTAL_CNT;
|
|
i++, addr += ADW_MC_RISC_Q_LIST_SIZE) {
|
|
|
|
/*
|
|
* Set the current RISC Queue List's
|
|
* RQL_FWD and RQL_BWD pointers in a
|
|
* one word write and set the state
|
|
* (RQL_STATE) to free.
|
|
*/
|
|
adw_lram_write_16(adw, addr, ((i + 1) | ((i - 1) << 8)));
|
|
adw_lram_write_8(adw, addr + RQL_STATE, ADW_MC_QS_FREE);
|
|
}
|
|
|
|
/*
|
|
* Set the Host and RISC Queue List pointers.
|
|
*
|
|
* Both sets of pointers are initialized with the same values:
|
|
* ADW_MC_RISC_Q_FIRST(0x01) and ADW_MC_RISC_Q_LAST (0xFF).
|
|
*/
|
|
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_READY, ADW_MC_RISC_Q_FIRST);
|
|
adw_lram_write_8(adw, ADW_MC_HOST_NEXT_DONE, ADW_MC_RISC_Q_LAST);
|
|
|
|
adw_lram_write_8(adw, ADW_MC_RISC_NEXT_READY, ADW_MC_RISC_Q_FIRST);
|
|
adw_lram_write_8(adw, ADW_MC_RISC_NEXT_DONE, ADW_MC_RISC_Q_LAST);
|
|
|
|
/*
|
|
* Set up the last RISC Queue List (255) with a NULL forward pointer.
|
|
*/
|
|
adw_lram_write_16(adw, addr, (ADW_MC_NULL_Q + ((i - 1) << 8)));
|
|
adw_lram_write_8(adw, addr + RQL_STATE, ADW_MC_QS_FREE);
|
|
|
|
adw_outb(adw, ADW_INTR_ENABLES,
|
|
ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
|
|
|
|
adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Send an idle command to the chip and optionally wait for completion.
|
|
*/
|
|
void
|
|
adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
|
|
{
|
|
int s;
|
|
|
|
adw->idle_command_cmp = 0;
|
|
|
|
s = splcam();
|
|
|
|
if (adw->idle_cmd != ADW_IDLE_CMD_COMPLETED)
|
|
printf("%s: Warning! Overlapped Idle Commands Attempted\n",
|
|
adw_name(adw));
|
|
adw->idle_cmd = cmd;
|
|
adw->idle_cmd_param = parameter;
|
|
|
|
/*
|
|
* Write the idle command value after the idle command parameter
|
|
* has been written to avoid a race condition. If the order is not
|
|
* followed, the microcode may process the idle command before the
|
|
* parameters have been written to LRAM.
|
|
*/
|
|
adw_lram_write_16(adw, ADW_MC_IDLE_PARA_STAT, parameter);
|
|
adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
|
|
splx(s);
|
|
}
|
|
|
|
/* Wait for an idle command to complete */
|
|
adw_idle_cmd_status_t
|
|
adw_idle_cmd_wait(struct adw_softc *adw)
|
|
{
|
|
u_int timeout;
|
|
adw_idle_cmd_status_t status;
|
|
int s;
|
|
|
|
/* Wait for up to 10 seconds for the command to complete */
|
|
timeout = 10000;
|
|
while (--timeout) {
|
|
if (adw->idle_command_cmp != 0)
|
|
break;
|
|
DELAY(1000);
|
|
}
|
|
|
|
if (timeout == 0)
|
|
panic("%s: Idle Command Timed Out!\n", adw_name(adw));
|
|
s = splcam();
|
|
status = adw_lram_read_16(adw, ADW_MC_IDLE_PARA_STAT);
|
|
splx(s);
|
|
return (status);
|
|
}
|