159 lines
4.9 KiB
C
159 lines
4.9 KiB
C
/*-
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* Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#define ASMC_MAXFANS 2
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struct asmc_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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int sc_nfan;
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int16_t sms_rest_x;
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int16_t sms_rest_y;
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int16_t sms_rest_z;
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struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
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struct sysctl_oid *sc_temp_tree;
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struct sysctl_oid *sc_sms_tree;
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struct sysctl_oid *sc_light_tree;
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struct asmc_model *sc_model;
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int sc_rid_port;
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int sc_rid_irq;
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struct resource *sc_ioport;
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struct resource *sc_irq;
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void *sc_cookie;
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int sc_sms_intrtype;
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struct taskqueue *sc_sms_tq;
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struct task sc_sms_task;
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};
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/*
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* Data port.
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*/
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#define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
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#define ASMC_DATAPORT_WRITE(sc, val) \
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bus_write_1(sc->sc_ioport, 0x00, val)
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#define ASMC_STATUS_MASK 0x0f
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/*
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* Command port.
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*/
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#define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
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#define ASMC_CMDPORT_WRITE(sc, val) \
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bus_write_1(sc->sc_ioport, 0x04, val)
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#define ASMC_CMDREAD 0x10
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#define ASMC_CMDWRITE 0x11
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/*
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* Interrupt port.
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*/
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#define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
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/* Number of keys */
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#define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
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/*
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* Fan control via SMC.
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*/
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#define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
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#define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
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#define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
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#define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
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#define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
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#define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
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#define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
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/*
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* Sudden Motion Sensor (SMS).
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*/
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#define ASMC_SMS_INIT1 0xe0
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#define ASMC_SMS_INIT2 0xf8
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#define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
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#define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
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#define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
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#define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
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#define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
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#define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
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#define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
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#define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
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#define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
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#define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
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#define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
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#define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
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/*
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* Keyboard backlight.
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*/
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#define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
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#define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
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#define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
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/*
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* Clamshell.
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*/
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#define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
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/*
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* Interrupt keys.
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*/
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#define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
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/*
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* Temperatures.
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*
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* First for MacBook, second for MacBook Pro, then for Intel Mac Mini.
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*
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*/
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#define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
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"TM0P", NULL }
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#define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
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"northbridge2", "heatsink1", \
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"heatsink2", "memory", }
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#define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
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"Northbridge Point 1", \
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"Northbridge Point 2", "Heatsink 1", \
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"Heatsink 2", "Memory Bank A", }
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#define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
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"TG0H", "TG0P", "TG0T", NULL }
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#define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
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"heatsink2", "memory", "graphics", \
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"graphicssink", "unknown", }
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#define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
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"Heatsink 1", "Heatsink 2", \
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"Memory Controller", \
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"Graphics Chip", "Graphics Heatsink", \
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"Unknown", }
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#define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
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#define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
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#define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
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"Northbridge Point 2" }
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