142 lines
4.1 KiB
C
142 lines
4.1 KiB
C
/*-
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* Copyright (c) 2018, Mellanox Technologies, Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MLX5_MLX5IO_H_
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#define _DEV_MLX5_MLX5IO_H_
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#include <sys/ioccom.h>
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struct mlx5_fwdump_reg {
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uint32_t addr;
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uint32_t val;
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};
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struct mlx5_fwdump_addr {
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uint32_t domain;
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uint8_t bus;
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uint8_t slot;
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uint8_t func;
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};
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struct mlx5_fwdump_get {
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struct mlx5_fwdump_addr devaddr;
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struct mlx5_fwdump_reg *buf;
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size_t reg_cnt;
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size_t reg_filled; /* out */
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};
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#define MLX5_FWDUMP_GET _IOWR('m', 1, struct mlx5_fwdump_get)
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#define MLX5_FWDUMP_RESET _IOW('m', 2, struct mlx5_fwdump_addr)
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#define MLX5_FWDUMP_FORCE _IOW('m', 3, struct mlx5_fwdump_addr)
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#ifndef _KERNEL
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#define MLX5_DEV_PATH _PATH_DEV"mlx5ctl"
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#endif
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enum mlx5_fpga_id {
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MLX5_FPGA_NEWTON = 0,
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MLX5_FPGA_EDISON = 1,
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MLX5_FPGA_MORSE = 2,
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MLX5_FPGA_MORSEQ = 3,
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};
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enum mlx5_fpga_image {
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MLX5_FPGA_IMAGE_USER = 0,
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MLX5_FPGA_IMAGE_FACTORY = 1,
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MLX5_FPGA_IMAGE_MAX = MLX5_FPGA_IMAGE_FACTORY,
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MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2,
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};
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enum mlx5_fpga_status {
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MLX5_FPGA_STATUS_SUCCESS = 0,
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MLX5_FPGA_STATUS_FAILURE = 1,
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MLX5_FPGA_STATUS_IN_PROGRESS = 2,
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MLX5_FPGA_STATUS_DISCONNECTED = 3,
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};
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struct mlx5_fpga_query {
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enum mlx5_fpga_image admin_image;
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enum mlx5_fpga_image oper_image;
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enum mlx5_fpga_status image_status;
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};
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enum mlx5_fpga_tee {
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MLX5_FPGA_TEE_DISABLE = 0,
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MLX5_FPGA_TEE_GENERATE_EVENT = 1,
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MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
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};
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enum mlx5_fpga_connect {
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MLX5_FPGA_CONNECT_QUERY = 0,
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MLX5_FPGA_CONNECT_DISCONNECT = 0x9,
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MLX5_FPGA_CONNECT_CONNECT = 0xA,
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};
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/**
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* enum mlx5_fpga_access_type - Enumerated the different methods possible for
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* accessing the device memory address space
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*/
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enum mlx5_fpga_access_type {
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/** Use the slow CX-FPGA I2C bus*/
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MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
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/** Use the fast 'shell QP' */
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MLX5_FPGA_ACCESS_TYPE_RDMA,
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/** Use the fastest available method */
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MLX5_FPGA_ACCESS_TYPE_DONTCARE,
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MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
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};
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#define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
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#define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
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struct mlx5_fpga_temperature {
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uint32_t temperature;
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uint32_t index;
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uint32_t tee;
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uint32_t max_temperature;
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uint32_t temperature_threshold_hi;
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uint32_t temperature_threshold_lo;
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uint32_t mte;
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uint32_t mtr;
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char sensor_name[16];
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};
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#define MLX5_FPGA_CAP_ARR_SZ 0x40
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#define MLX5_FPGA_ACCESS_TYPE _IOWINT('m', 0x80)
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#define MLX5_FPGA_LOAD _IOWINT('m', 0x81)
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#define MLX5_FPGA_RESET _IO('m', 0x82)
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#define MLX5_FPGA_IMAGE_SEL _IOWINT('m', 0x83)
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#define MLX5_FPGA_QUERY _IOR('m', 0x84, struct mlx5_fpga_query)
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#define MLX5_FPGA_CAP _IOR('m', 0x85, uint32_t[MLX5_FPGA_CAP_ARR_SZ])
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#define MLX5_FPGA_TEMPERATURE _IOWR('m', 0x86, struct mlx5_fpga_temperature)
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#define MLX5_FPGA_CONNECT _IOWR('m', 0x87, enum mlx5_fpga_connect)
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#define MLX5_FPGA_TOOLS_NAME_SUFFIX "_mlx5_fpga_tools"
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#endif
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