47d8c9cde3
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit) |
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| .. | ||
| siba_bhndb.c | ||
| siba_erom.c | ||
| siba_nexus.c | ||
| siba_subr.c | ||
| siba.c | ||
| siba.h | ||
| sibareg.h | ||
| sibavar.h | ||