72e64728c9
Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
122 lines
4.1 KiB
C
122 lines
4.1 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __XLP_PCIBUS_H__
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#define __XLP_PCIBUS_H__
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#define MSI_MIPS_ADDR_BASE 0xfee00000
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/* MSI support */
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#define MSI_MIPS_ADDR_DEST 0x000ff000
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#define MSI_MIPS_ADDR_RH 0x00000008
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#define MSI_MIPS_ADDR_RH_OFF 0x00000000
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#define MSI_MIPS_ADDR_RH_ON 0x00000008
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#define MSI_MIPS_ADDR_DM 0x00000004
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#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
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#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
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/* Fields in data for Intel MSI messages. */
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#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
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#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
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#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
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#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
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#define MSI_MIPS_DATA_DEASSERT 0x00000000
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#define MSI_MIPS_DATA_ASSERT 0x00004000
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#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
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#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
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#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
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#define MSI_MIPS_DATA_INTVEC 0x000000ff
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/* PCIE Memory and IO regions */
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#define PCIE_MEM_BASE 0xd0000000ULL
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#define PCIE_MEM_LIMIT 0xdfffffffULL
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#define PCIE_IO_BASE 0x14000000ULL
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#define PCIE_IO_LIMIT 0x15ffffffULL
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#define PCIE_BRIDGE_CMD 0x1
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#define PCIE_BRIDGE_MSI_CAP 0x14
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#define PCIE_BRIDGE_MSI_ADDRL 0x15
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#define PCIE_BRIDGE_MSI_ADDRH 0x16
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#define PCIE_BRIDGE_MSI_DATA 0x17
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/* XLP Global PCIE configuration space registers */
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#define PCIE_BYTE_SWAP_MEM_BASE 0x247
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#define PCIE_BYTE_SWAP_MEM_LIM 0x248
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#define PCIE_BYTE_SWAP_IO_BASE 0x249
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#define PCIE_BYTE_SWAP_IO_LIM 0x24A
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#define PCIE_MSI_STATUS 0x25A
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#define PCIE_MSI_EN 0x25B
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#define PCIE_INT_EN0 0x261
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/* PCIE_MSI_EN */
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#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
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/* PCIE_INT_EN0 */
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#define PCIE_MSI_INT_EN (1 << 9)
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/* XXXJC: Ax workaround */
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#define PCIE_LINK0_IRT 78
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_pcie_base(node, inst) \
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nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
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#define nlm_get_pcie_regbase(node, inst) \
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(nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
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static __inline int
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xlp_pcie_link_irt(int link)
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{
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if ((link < 0) || (link > 3))
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return (-1);
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return (PCIE_LINK0_IRT + link);
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}
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/*
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* Build Intel MSI message and data values from a source. AMD64 systems
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* seem to be compatible, so we use the same function for both.
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*/
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#define MIPS_MSI_ADDR(cpu) \
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(MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
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MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
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#define MIPS_MSI_DATA(irq) \
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(MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
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MSI_MIPS_DATA_ASSERT | (irq))
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#endif
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#endif /* __XLP_PCIBUS_H__ */
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