69 lines
3.3 KiB
C
69 lines
3.3 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_PIOREG_H
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#define ARM_AT91_AT91_PIOREG_H
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/* Registers */
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#define PIO_PER 0x00 /* PIO Enable Register */
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#define PIO_PDR 0x04 /* PIO Disable Register */
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#define PIO_PSR 0x08 /* PIO Status Register */
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/* 0x0c reserved */
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#define PIO_OER 0x10 /* PIO Output Enable Register */
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#define PIO_ODR 0x14 /* PIO Output Disable Register */
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#define PIO_OSR 0x18 /* PIO Output Status Register */
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/* 0x1c reserved */
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#define PIO_IFER 0x20 /* PIO Glitch Input Enable Register */
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#define PIO_IFDR 0x24 /* PIO Glitch Input Disable Register */
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#define PIO_IFSR 0x28 /* PIO Glitch Input Status Register */
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/* 0x2c reserved */
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#define PIO_SODR 0x30 /* PIO Set Output Data Register */
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#define PIO_CODR 0x34 /* PIO Clear Output Data Register */
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#define PIO_ODSR 0x38 /* PIO Output Data Status Register */
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#define PIO_PDSR 0x3c /* PIO Pin Data Status Register */
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#define PIO_IER 0x40 /* PIO Interrupt Enable Register */
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#define PIO_IDR 0x44 /* PIO Interrupt Disable Register */
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#define PIO_IMR 0x48 /* PIO Interrupt Mask Register */
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#define PIO_ISR 0x4c /* PIO Interrupt Status Register */
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#define PIO_MDER 0x50 /* PIO Multi-Driver Enable Register */
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#define PIO_MDDR 0x54 /* PIO Multi-Driver Disable Register */
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#define PIO_MDSR 0x58 /* PIO Multi-Driver Status Register */
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/* 0x5c reserved */
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#define PIO_PUDR 0x60 /* PIO Pull-up Disable Register */
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#define PIO_PUER 0x64 /* PIO Pull-up Enable Register */
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#define PIO_PUSR 0x68 /* PIO Pull-up Status Register */
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/* 0x6c reserved */
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#define PIO_ASR 0x70 /* PIO Peripheral A Select Register */
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#define PIO_BSR 0x74 /* PIO Peripheral B Select Register */
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#define PIO_ABSR 0x78 /* PIO AB Status Register */
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/* 0x7c-0x9c reserved */
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#define PIO_OWER 0xa0 /* PIO Output Write Enable Register */
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#define PIO_OWDR 0xa4 /* PIO Output Write Disable Register */
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#define PIO_OWSR 0xa8 /* PIO Output Write Status Register */
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/* 0xac reserved */
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#endif /* ARM_AT91_AT91_PIOREG_H */
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