58f9305267
o Add FPGA memory window to static dev mappings o Fix whitespace
117 lines
2.8 KiB
C
117 lines
2.8 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <machine/devmap.h>
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#include <machine/machdep.h>
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#include <machine/platform.h>
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vm_offset_t
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platform_lastaddr(void)
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{
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return (arm_devmap_lastaddr());
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}
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void
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platform_probe_and_attach(void)
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{
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}
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void
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platform_gpio_init(void)
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{
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}
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void
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platform_late_init(void)
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{
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}
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int
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platform_devmap_init(void)
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{
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/* UART */
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arm_devmap_add_entry(0xffc00000, 0x100000);
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/*
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* USB OTG
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*
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* We use static device map for USB due to some bug in the Altera
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* which throws Translation Fault (P) exception on high load.
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* It might be caused due to some power save options being turned
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* on or something else.
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*/
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arm_devmap_add_entry(0xffb00000, 0x100000);
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/* dwmmc */
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arm_devmap_add_entry(0xff700000, 0x100000);
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/* scu */
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arm_devmap_add_entry(0xfff00000, 0x100000);
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/* FPGA memory window, 256MB */
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arm_devmap_add_entry(0xd0000000, 0x10000000);
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return (0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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