b5afe950d0
preparation for tsunami support. Previous chipsets' direct-mapped DMA mask was always 1024*1024*1024. The Tsunami chipset needs it to be 2*1024*1024*1024 These changes should not affect the i386 port Reviewed by: Doug Rabson <dfr@nlsystems.com>
243 lines
7.7 KiB
C
243 lines
7.7 KiB
C
/*
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*
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* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
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* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
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* from: i386 pmap.h,v 1.54 1997/11/20 19:30:35 bde Exp
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* $Id: pmap.h,v 1.3 1998/08/23 16:05:55 dfr Exp $
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*/
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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/*
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* Define meanings for a few software bits in the pte
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*/
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#define PG_V ALPHA_PTE_VALID
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#define PG_FOR ALPHA_PTE_FAULT_ON_READ
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#define PG_FOW ALPHA_PTE_FAULT_ON_WRITE
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#define PG_FOE ALPHA_PTE_FAULT_ON_EXECUTE
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#define PG_ASM ALPHA_PTE_ASM
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#define PG_GH ALPHA_PTE_GRANULARITY
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#define PG_KRE ALPHA_PTE_KR
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#define PG_URE ALPHA_PTE_UR
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#define PG_KWE ALPHA_PTE_KW
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#define PG_UWE ALPHA_PTE_UW
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#define PG_PROT ALPHA_PTE_PROT
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#define PG_SHIFT 32
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#define PG_W 0x00010000 /* software wired */
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#define PG_MANAGED 0x00020000 /* software managed */
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/*
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* Pte related macros
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*/
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#define VADDR(l1, l2, l3) (((l1) << ALPHA_L1SHIFT) \
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+ ((l2) << ALPHA_L2SHIFT) \
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+ ((l3) << ALPHA_L3SHIFT)
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#ifndef NKPT
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#define NKPT 9 /* initial number of kernel page tables */
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#endif
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#define NKLEV2MAPS 255 /* max number of lev2 page tables */
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#define NKLEV3MAPS (NKLEV2MAPS << ALPHA_PTSHIFT) /* max number of lev3 page tables */
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/*
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* The *PTDI values control the layout of virtual memory
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*
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* XXX This works for now, but I am not real happy with it, I'll fix it
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* right after I fix locore.s and the magic 28K hole
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*
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* SMP_PRIVPAGES: The per-cpu address space is 0xff80000 -> 0xffbfffff
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*/
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#define PTLEV1I (NPTEPG-1) /* Lev0 entry that points to Lev0 */
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#define K0SEGLEV1I (NPTEPG/2)
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#define K1SEGLEV1I (K0SEGLEV1I+(NPTEPG/4))
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#define NUSERLEV2MAPS (NPTEPG/2)
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#define NUSERLEV3MAPS (NUSERLEV2MAPS << ALPHA_PTSHIFT)
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#ifndef LOCORE
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#include <sys/queue.h>
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typedef alpha_pt_entry_t pt_entry_t;
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#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
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/*
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* Address of current address space page table maps
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*/
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#ifdef KERNEL
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extern pt_entry_t PTmap[]; /* lev3 page tables */
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extern pt_entry_t PTlev2[]; /* lev2 page tables */
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extern pt_entry_t PTlev1[]; /* lev1 page table */
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extern pt_entry_t PTlev1pte; /* pte that maps lev1 page table */
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#endif
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#ifdef KERNEL
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/*
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* virtual address to page table entry and
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* to physical address.
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* Note: this work recursively, thus vtopte of a pte will give
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* the corresponding lev1 that in turn maps it.
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*/
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#define vtopte(va) (PTmap + (alpha_btop(va) \
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& ((1 << 3*ALPHA_PTSHIFT)-1)))
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/*
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* Routine: pmap_kextract
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* Function:
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* Extract the physical page address associated
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* kernel virtual address.
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*/
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static __inline vm_offset_t
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pmap_kextract(vm_offset_t va)
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{
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vm_offset_t pa;
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if (va >= ALPHA_K0SEG_BASE && va <= ALPHA_K0SEG_END)
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pa = ALPHA_K0SEG_TO_PHYS(va);
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else
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pa = alpha_ptob(ALPHA_PTE_TO_PFN(*vtopte(va)))
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| (va & PAGE_MASK);
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return pa;
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}
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#define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
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extern vm_offset_t alpha_XXX_dmamap_or;
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static __inline vm_offset_t
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alpha_XXX_dmamap(vm_offset_t va)
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{
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return (pmap_kextract(va) | alpha_XXX_dmamap_or);
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}
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#endif /* KERNEL */
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/*
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* Pmap stuff
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*/
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struct pv_entry;
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typedef struct {
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int pv_list_count;
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struct vm_page *pv_vm_page;
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int pv_flags;
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TAILQ_HEAD(,pv_entry) pv_list;
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} pv_table_t;
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#define PV_TABLE_MOD 0x01 /* modified */
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#define PV_TABLE_REF 0x02 /* referenced */
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struct pmap {
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pt_entry_t *pm_lev1; /* KVA of lev0map */
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vm_object_t pm_pteobj; /* Container for pte's */
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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int pm_count; /* reference count */
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int pm_flags; /* pmap flags */
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int pm_active; /* active flag */
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int pm_asn; /* address space number */
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u_int pm_asngen; /* generation number of pm_asn */
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struct pmap_statistics pm_stats; /* pmap statistics */
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struct vm_page *pm_ptphint; /* pmap ptp hint */
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};
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#define pmap_resident_count(pmap) (pmap)->pm_stats.resident_count
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#define PM_FLAG_LOCKED 0x1
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#define PM_FLAG_WANTED 0x2
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typedef struct pmap *pmap_t;
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#ifdef KERNEL
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extern pmap_t kernel_pmap;
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#endif
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/*
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* For each vm_page_t, there is a list of all currently valid virtual
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* mappings of that page. An entry is a pv_entry_t, the list is pv_table.
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*/
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typedef struct pv_entry {
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pmap_t pv_pmap; /* pmap where mapping lies */
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vm_offset_t pv_va; /* virtual address for mapping */
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TAILQ_ENTRY(pv_entry) pv_list;
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TAILQ_ENTRY(pv_entry) pv_plist;
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vm_page_t pv_ptem; /* VM page for pte */
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} *pv_entry_t;
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#define PV_ENTRY_NULL ((pv_entry_t) 0)
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#define PV_CI 0x01 /* all entries must be cache inhibited */
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#define PV_PTPAGE 0x02 /* entry maps a page table page */
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#ifdef KERNEL
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extern caddr_t CADDR1;
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extern pt_entry_t *CMAP1;
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extern vm_offset_t avail_end;
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extern vm_offset_t avail_start;
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extern vm_offset_t clean_eva;
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extern vm_offset_t clean_sva;
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extern vm_offset_t phys_avail[];
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extern char *ptvmmap; /* poor name! */
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extern vm_offset_t virtual_avail;
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extern vm_offset_t virtual_end;
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vm_offset_t pmap_steal_memory __P((vm_size_t));
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void pmap_bootstrap __P((vm_offset_t, u_int));
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void pmap_setdevram __P((unsigned long long basea, vm_offset_t sizea));
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int pmap_uses_prom_console __P((void));
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pmap_t pmap_kernel __P((void));
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void *pmap_mapdev __P((vm_offset_t, vm_size_t));
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unsigned *pmap_pte __P((pmap_t, vm_offset_t)) __pure2;
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vm_page_t pmap_use_pt __P((pmap_t, vm_offset_t));
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void pmap_set_opt __P((unsigned *));
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void pmap_set_opt_bsp __P((void));
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void pmap_deactivate __P((struct proc *p));
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void pmap_emulate_reference __P((struct proc *p, vm_offset_t v, int user, int write));
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#endif /* KERNEL */
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#endif /* !LOCORE */
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#endif /* !_MACHINE_PMAP_H_ */
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