Jayachandran C. b2ef3bae84 Initialize GIC[DR]_IGROUPRn registers for GICv3 ... In case where GICD_CTLR.DS is 1, the IGROUPR registers are RW in non-secure state and has to be initialized to 1 for the corresponding interrupts to be delivered as Group 1 interrupts. Update gic_v3_dist_init() and gic_v3_redist_init() to initialize GICD_IGROUPRn and GICR_IGROUPRn respectively to address this. The registers can be set unconditionally since the writes are ignored in non-secure state when GICD_CTLR.DS is 0. This fixes the hang on boot seen when running qemu-system-aarch64 with machine virt,gic-version=3		2016-12-18 08:31:01 +00:00
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acpica	Add support to find the arm64 serial using the ACPI tables. This uses the	2016-11-21 19:26:58 +00:00
arm64	Initialize GIC[DR]_IGROUPRn registers for GICv3	2016-12-18 08:31:01 +00:00
cavium	Fix the alloc function the ThunderX PCIe driver calls, the previous	2016-11-30 14:17:06 +00:00
cloudabi64	Convert pointers obtained from the threadattr_t structure with TO_PTR().	2016-08-24 10:13:18 +00:00
conf	Enable ACPI on arm64. It's not yet functional, but it will help keeping the	2016-12-12 18:13:03 +00:00
include	Move the stored signal mask later in the jump buf. It was being clobbered	2016-12-06 13:46:12 +00:00