cdfefa0ba0
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
363 lines
13 KiB
C
363 lines
13 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/* This file contains support functions for the Cortina IXF18201 SPI->XAUI dual
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** MAC. The IXF18201 has dual SPI and dual XAUI interfaces to provide 2 10 gigabit
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** interfaces.
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** This file supports the EBT5810 evaluation board. To support a different board,
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** the 16 bit read/write functions would need to be customized for that board, and the
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** IXF18201 may need to be initialized differently as well.
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**
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** The IXF18201 and Octeon are configured for 2 SPI channels per interface (ports 0/1, and 16/17).
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** Ports 0 and 16 are the ports that are connected to the XAUI MACs (which are connected to the SFP+ modules)
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** Ports 1 and 17 are connected to the hairpin loopback port on the IXF SPI interface. All packets sent out
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** of these ports are looped back the same port they were sent on. The loopback ports are always enabled.
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**
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** The MAC address filtering on the IXF is not enabled. Link up/down events are not detected, only SPI status
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** is monitored by default, which is independent of the XAUI/SFP+ link status.
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**
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**
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*/
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#include "cvmx.h"
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#include "cvmx-swap.h"
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#define PAL_BASE (1ull << 63 | 0x1d030000)
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#define IXF_ADDR_HI (PAL_BASE + 0xa)
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#define IXF_ADDR_LO (PAL_BASE + 0xb)
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#define IXF_ADDR_16 IXF_ADDR_HI /* 16 bit access */
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#define IXF_WR_DATA_HI (PAL_BASE + 0xc)
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#define IXF_WR_DATA_LO (PAL_BASE + 0xd)
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#define IXF_WR_DATA_16 IXF_WR_DATA_HI
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#define IXF_RD_DATA_HI (PAL_BASE + 0x10)
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#define IXF_RD_DATA_LO (PAL_BASE + 0x11)
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#define IXF_RD_DATA_16 IXF_RD_DATA_HI
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#define IXF_TRANS_TYPE (PAL_BASE + 0xe)
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#define IXF_TRANS_STATUS (PAL_BASE + 0xf)
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uint16_t cvmx_ixf18201_read16(uint16_t reg_addr)
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{
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cvmx_write64_uint16(IXF_ADDR_16, reg_addr);
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cvmx_write64_uint8(IXF_TRANS_TYPE, 1); // Do read
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cvmx_wait(800000);
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/* Read result */
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return(cvmx_read64_uint16(IXF_RD_DATA_16));
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}
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void cvmx_ixf18201_write16(uint16_t reg_addr, uint16_t data)
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{
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cvmx_write64_uint16(IXF_ADDR_16, reg_addr);
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cvmx_write64_uint16(IXF_WR_DATA_16, data);
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cvmx_write64_uint8(IXF_TRANS_TYPE, 0);
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cvmx_wait(800000);
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}
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uint32_t cvmx_ixf18201_read32(uint16_t reg_addr)
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{
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uint32_t hi, lo;
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if (reg_addr & 0x1)
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{
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return(0xdeadbeef);
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}
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lo = cvmx_ixf18201_read16(reg_addr);
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hi = cvmx_ixf18201_read16(reg_addr + 1);
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return((hi << 16) | lo);
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}
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void cvmx_ixf18201_write32(uint16_t reg_addr, uint32_t data)
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{
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uint16_t hi, lo;
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if (reg_addr & 0x1)
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{
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return;
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}
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lo = data & 0xFFFF;
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hi = data >> 16;
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cvmx_ixf18201_write16(reg_addr, lo);
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cvmx_ixf18201_write16(reg_addr + 1, hi);
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}
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#define IXF_REG_MDI_CMD_ADDR1 0x310E
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#define IXF_REG_MDI_RD_WR1 0x3110
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void cvmx_ixf18201_mii_write(int mii_addr, int mmd, uint16_t reg, uint16_t val)
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{
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uint32_t cmd_val = 0;
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cmd_val = reg;
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cmd_val |= 0x0 << 26; // Set address operation
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cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
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cmd_val |= (mmd & 0x1f) << 16; // Set MMD
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cmd_val |= 1 << 30; // Do operation
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cmd_val |= 1 << 31; // enable in progress bit
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/* Set up address */
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cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
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while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
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; /* Wait for operation to complete */
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cvmx_ixf18201_write32(IXF_REG_MDI_RD_WR1, val);
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/* Do read operation */
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cmd_val = 0;
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cmd_val |= 0x1 << 26; // Set write operation
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cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
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cmd_val |= (mmd & 0x1f) << 16; // Set MMD
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cmd_val |= 1 << 30; // Do operation
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cmd_val |= 1 << 31; // enable in progress bit
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cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
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while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
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; /* Wait for operation to complete */
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}
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int cvmx_ixf18201_mii_read(int mii_addr, int mmd, uint16_t reg)
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{
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uint32_t cmd_val = 0;
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cmd_val = reg;
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cmd_val |= 0x0 << 26; // Set address operation
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cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
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cmd_val |= (mmd & 0x1f) << 16; // Set MMD
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cmd_val |= 1 << 30; // Do operation
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cmd_val |= 1 << 31; // enable in progress bit
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/* Set up address */
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cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
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while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
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; /* Wait for operation to complete */
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/* Do read operation */
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cmd_val = 0;
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cmd_val |= 0x3 << 26; // Set read operation
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cmd_val |= (mii_addr & 0x1f) << 21; // Set PHY addr
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cmd_val |= (mmd & 0x1f) << 16; // Set MMD
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cmd_val |= 1 << 30; // Do operation
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cmd_val |= 1 << 31; // enable in progress bit
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cvmx_ixf18201_write32(IXF_REG_MDI_CMD_ADDR1, cmd_val);
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while (cvmx_ixf18201_read32(IXF_REG_MDI_CMD_ADDR1) & ( 1 << 30))
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; /* Wait for operation to complete */
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cmd_val = cvmx_ixf18201_read32(IXF_REG_MDI_RD_WR1);
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return(cmd_val >> 16);
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}
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int cvmx_ixf18201_init(void)
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{
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int index; /* For indexing the two 'ports' on ixf */
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int offset;
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/* Reset IXF, and take all blocks out of reset */
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/*
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Initializing...
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PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0000, new: 0x0001
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PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0001, new: 0x0000
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PP0:~CONSOLE-> **** LLM201(Lochlomond) Driver loaded ****
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PP0:~CONSOLE-> LLM201 Driver - Released on Tue Aug 28 09:51:30 2007.
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PP0:~CONSOLE-> retval is: 0
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PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0000, new: 0x0001
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PP0:~CONSOLE-> Changing register value, addr 0x0003, old: 0x0001, new: 0x0000
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PP0:~CONSOLE-> Brought all blocks out of reset
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PP0:~CONSOLE-> Getting default config.
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*/
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cvmx_ixf18201_write16(0x0003, 0x0001);
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cvmx_ixf18201_write16(0x0003, 0);
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/*
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PP0:~CONSOLE-> Changing register value, addr 0x0000, old: 0x4014, new: 0x4010
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PP0:~CONSOLE-> Changing register value, addr 0x0000, old: 0x4010, new: 0x4014
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PP0:~CONSOLE-> Changing register value, addr 0x0004, old: 0x01ff, new: 0x0140
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PP0:~CONSOLE-> Changing register value, addr 0x0009, old: 0x007f, new: 0x0000
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*/
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cvmx_ixf18201_write16(0x0000, 0x4010);
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cvmx_ixf18201_write16(0x0000, 0x4014);
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cvmx_ixf18201_write16(0x0004, 0x0140);
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cvmx_ixf18201_write16(0x0009, 0);
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/*
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PP0:~CONSOLE-> Changing register value, addr 0x000e, old: 0x0000, new: 0x000f
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PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0000, new: 0x0004
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PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0004, new: 0x0006
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PP0:~CONSOLE-> Changing register value, addr 0x000e, old: 0x000f, new: 0x00f0
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PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0006, new: 0x0040
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PP0:~CONSOLE-> Changing register value, addr 0x000f, old: 0x0040, new: 0x0060
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*/
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// skip GPIO, 0xe/0xf
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/*
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PP0:~CONSOLE-> Changing register value, addr 0x3100, old: 0x57fb, new: 0x7f7b
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PP0:~CONSOLE-> Changing register value, addr 0x3600, old: 0x57fb, new: 0x7f7b
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PP0:~CONSOLE-> Changing register value, addr 0x3005, old: 0x8010, new: 0x0040
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PP0:~CONSOLE-> Changing register value, addr 0x3006, old: 0x061a, new: 0x0000
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PP0:~CONSOLE-> Changing register value, addr 0x3505, old: 0x8010, new: 0x0040
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PP0:~CONSOLE-> Changing register value, addr 0x3506, old: 0x061a, new: 0x0000
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*/
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for (index = 0; index < 2;index++ )
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{
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offset = 0x500 * index;
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cvmx_ixf18201_write32(0x3100 + offset, 0x47f7b);
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cvmx_ixf18201_write16(0x3005 + offset, 0x0040);
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cvmx_ixf18201_write16(0x3006 + offset, 0);
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}
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/*PP0:~CONSOLE-> *** SPI soft reset ***, block id: 0
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PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0xf980, new: 0xf9c0
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PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0xa6f0, new: 0x36f0
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PP0:~CONSOLE-> Changing register value, addr 0x3000, old: 0x0080, new: 0x0060
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PP0:~CONSOLE-> Changing register value, addr 0x3002, old: 0x0200, new: 0x0040
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PP0:~CONSOLE-> Changing register value, addr 0x3003, old: 0x0100, new: 0x0000
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PP0:~CONSOLE-> Changing register value, addr 0x30c2, old: 0x0080, new: 0x0060
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PP0:~CONSOLE-> Changing register value, addr 0x300a, old: 0x0800, new: 0x0000
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PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0xf9c0, new: 0x89c0
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PP0:~CONSOLE-> Changing register value, addr 0x3016, old: 0x0000, new: 0x0010
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PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0x36f0, new: 0x3610
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PP0:~CONSOLE-> Changing register value, addr 0x3012, old: 0x0000, new: 0x0010
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PP0:~CONSOLE-> Changing register value, addr 0x3007, old: 0x89c0, new: 0x8980
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PP0:~CONSOLE-> Changing register value, addr 0x3008, old: 0x3610, new: 0xa210
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PP0:~CONSOLE->
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*/
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for (index = 0; index < 2;index++ )
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{
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offset = 0x500 * index;
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int cal_len_min_1 = 0; /* Calendar length -1. Must match number
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** of ports configured for interface.*/
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cvmx_ixf18201_write16(0x3007 + offset, 0x81c0 | (cal_len_min_1 << 11));
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cvmx_ixf18201_write16(0x3008 + offset, 0x3600 | (cal_len_min_1 << 4));
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cvmx_ixf18201_write16(0x3000 + offset, 0x0060);
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cvmx_ixf18201_write16(0x3002 + offset, 0x0040);
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cvmx_ixf18201_write16(0x3003 + offset, 0x0000);
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cvmx_ixf18201_write16(0x30c2 + offset, 0x0060);
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cvmx_ixf18201_write16(0x300a + offset, 0x0000);
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cvmx_ixf18201_write16(0x3007 + offset, 0x81c0 | (cal_len_min_1 << 11));
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cvmx_ixf18201_write16(0x3016 + offset, 0x0010);
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cvmx_ixf18201_write16(0x3008 + offset, 0x3600 | (cal_len_min_1 << 4));
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cvmx_ixf18201_write16(0x3012 + offset, 0x0010);
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cvmx_ixf18201_write16(0x3007 + offset, 0x8180 | (cal_len_min_1 << 11));
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cvmx_ixf18201_write16(0x3008 + offset, 0xa200 | (cal_len_min_1 << 4));
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cvmx_ixf18201_write16(0x3090 + offset, 0x0301); /* Enable hairpin loopback */
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}
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/*
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PP0:~CONSOLE-> Changing register value, addr 0x0004, old: 0x0140, new: 0x1fff
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PP0:~CONSOLE-> Changing register value, addr 0x0009, old: 0x0000, new: 0x007f
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PP0:~CONSOLE-> Changing register value, addr 0x310b, old: 0x0004, new: 0xffff
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PP0:~CONSOLE-> Changing register value, addr 0x310a, old: 0x7f7b, new: 0xffff
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*/
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cvmx_ixf18201_write16(0x0004, 0x1fff);
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cvmx_ixf18201_write16(0x0009, 0x007f);
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#if 0
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/* MDI autoscan */
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cvmx_ixf18201_write16(0x310b, 0xffff);
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cvmx_ixf18201_write16(0x310a, 0xffff);
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#endif
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/*
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*** 32 bit register, trace only captures part of it...
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PP0:~CONSOLE-> Changing register value, addr 0x3100, old: 0x7f7b, new: 0x7f78
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PP0:~CONSOLE-> Changing register value, addr 0x3600, old: 0x7f7b, new: 0x7f78
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*/
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for (index = 0; index < 2;index++ )
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{
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offset = 0x500 * index;
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cvmx_ixf18201_write32(0x3100 + offset, 0x47f7c); /* Also enable jumbo frames */
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/* Set max packet size to 9600 bytes, max supported by IXF18201 */
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cvmx_ixf18201_write32(0x3114 + offset, 0x25800000);
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}
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cvmx_wait(100000000);
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/* Now reset the PCS blocks in the phy. This seems to be required after
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** bringing up the Cortina. */
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cvmx_ixf18201_mii_write(1, 3, 0, 0x8000);
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cvmx_ixf18201_mii_write(5, 3, 0, 0x8000);
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return 1;
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}
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