587 lines
26 KiB
C
587 lines
26 KiB
C
/*-
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* Copyright (c) 1998 - 2005 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* ATA register defines */
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#define ATA_DATA 0 /* (RW) data */
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#define ATA_FEATURE 1 /* (W) feature */
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#define ATA_F_DMA 0x01 /* enable DMA */
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#define ATA_F_OVL 0x02 /* enable overlap */
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#define ATA_COUNT 2 /* (W) sector count */
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#define ATA_SECTOR 3 /* (RW) sector # */
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#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
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#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
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#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
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#define ATA_D_LBA 0x40 /* use LBA addressing */
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#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
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#define ATA_COMMAND 7 /* (W) command */
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#define ATA_ERROR 8 /* (R) error */
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#define ATA_E_ILI 0x01 /* illegal length */
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#define ATA_E_NM 0x02 /* no media */
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#define ATA_E_ABORT 0x04 /* command aborted */
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#define ATA_E_MCR 0x08 /* media change request */
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#define ATA_E_IDNF 0x10 /* ID not found */
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#define ATA_E_MC 0x20 /* media changed */
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#define ATA_E_UNC 0x40 /* uncorrectable data */
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#define ATA_E_ICRC 0x80 /* UDMA crc error */
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#define ATA_E_MASK 0x0f /* error mask */
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#define ATA_SK_MASK 0xf0 /* sense key mask */
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#define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */
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#define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */
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#define ATA_SK_NOT_READY 0x20 /* no access to drive */
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#define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */
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#define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */
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#define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */
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#define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */
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#define ATA_SK_DATA_PROTECT 0x70 /* write protect */
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#define ATA_SK_BLANK_CHECK 0x80 /* blank check */
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#define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */
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#define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */
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#define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */
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#define ATA_SK_EQUAL 0xc0 /* equal */
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#define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */
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#define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */
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#define ATA_SK_RESERVED 0xf0
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#define ATA_IREASON 9 /* (R) interrupt reason */
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#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
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#define ATA_I_IN 0x02 /* read (1) | write (0) */
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#define ATA_I_RELEASE 0x04 /* released bus (1) */
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#define ATA_I_TAGMASK 0xf8 /* tag mask */
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#define ATA_STATUS 10 /* (R) status */
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#define ATA_ALTSTAT 11 /* (R) alternate status */
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#define ATA_S_ERROR 0x01 /* error */
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#define ATA_S_INDEX 0x02 /* index */
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#define ATA_S_CORR 0x04 /* data corrected */
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#define ATA_S_DRQ 0x08 /* data request */
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#define ATA_S_DSC 0x10 /* drive seek completed */
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#define ATA_S_SERVICE 0x10 /* drive needs service */
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#define ATA_S_DWF 0x20 /* drive write fault */
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#define ATA_S_DMA 0x20 /* DMA ready */
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#define ATA_S_READY 0x40 /* drive ready */
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#define ATA_S_BUSY 0x80 /* busy */
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#define ATA_CONTROL 12 /* (W) control */
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#define ATA_CTLOFFSET 0x206 /* control register offset */
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#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */
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#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */
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#define ATA_A_IDS 0x02 /* disable interrupts */
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#define ATA_A_RESET 0x04 /* RESET controller */
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#define ATA_A_4BIT 0x08 /* 4 head bits */
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#define ATA_A_HOB 0x80 /* High Order Byte enable */
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/* SATA register defines */
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#define ATA_SSTATUS 13
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#define ATA_SS_DET_MASK 0x0000000f
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#define ATA_SS_DET_NO_DEVICE 0x00000000
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#define ATA_SS_DET_DEV_PRESENT 0x00000001
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#define ATA_SS_DET_PHY_ONLINE 0x00000003
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#define ATA_SS_DET_PHY_OFFLINE 0x00000004
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#define ATA_SS_SPD_MASK 0x000000f0
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#define ATA_SS_SPD_NO_SPEED 0x00000000
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#define ATA_SS_SPD_GEN1 0x00000010
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#define ATA_SS_SPD_GEN2 0x00000020
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#define ATA_SS_IPM_MASK 0x00000f00
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#define ATA_SS_IPM_NO_DEVICE 0x00000000
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#define ATA_SS_IPM_ACTIVE 0x00000100
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#define ATA_SS_IPM_PARTIAL 0x00000200
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#define ATA_SS_IPM_SLUMBER 0x00000600
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#define ATA_SS_CONWELL_MASK \
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(ATA_SS_DET_MASK|ATA_SS_SPD_MASK|ATA_SS_IPM_MASK)
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#define ATA_SS_CONWELL_GEN1 \
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(ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN1|ATA_SS_IPM_ACTIVE)
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#define ATA_SS_CONWELL_GEN2 \
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(ATA_SS_DET_PHY_ONLINE|ATA_SS_SPD_GEN2|ATA_SS_IPM_ACTIVE)
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#define ATA_SERROR 14
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#define ATA_SE_DATA_CORRECTED 0x00000001
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#define ATA_SE_COMM_CORRECTED 0x00000002
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#define ATA_SE_DATA_ERR 0x00000100
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#define ATA_SE_COMM_ERR 0x00000200
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#define ATA_SE_PROT_ERR 0x00000400
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#define ATA_SE_HOST_ERR 0x00000800
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#define ATA_SE_PHY_CHANGED 0x00010000
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#define ATA_SE_PHY_IERROR 0x00020000
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#define ATA_SE_COMM_WAKE 0x00040000
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#define ATA_SE_DECODE_ERR 0x00080000
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#define ATA_SE_PARITY_ERR 0x00100000
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#define ATA_SE_CRC_ERR 0x00200000
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#define ATA_SE_HANDSHAKE_ERR 0x00400000
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#define ATA_SE_LINKSEQ_ERR 0x00800000
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#define ATA_SE_TRANSPORT_ERR 0x01000000
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#define ATA_SE_UNKNOWN_FIS 0x02000000
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#define ATA_SCONTROL 15
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#define ATA_SC_DET_MASK 0x0000000f
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#define ATA_SC_DET_IDLE 0x00000000
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#define ATA_SC_DET_RESET 0x00000001
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#define ATA_SC_DET_DISABLE 0x00000004
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#define ATA_SC_SPD_MASK 0x000000f0
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#define ATA_SC_SPD_NO_SPEED 0x00000000
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#define ATA_SC_SPD_SPEED_GEN1 0x00000010
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#define ATA_SC_SPD_SPEED_GEN2 0x00000020
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#define ATA_SC_IPM_MASK 0x00000f00
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#define ATA_SC_IPM_NONE 0x00000000
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#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
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#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
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/* DMA register defines */
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#define ATA_DMA_ENTRIES 256
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#define ATA_DMA_EOT 0x80000000
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#define ATA_BMCMD_PORT 16
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#define ATA_BMCMD_START_STOP 0x01
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#define ATA_BMCMD_WRITE_READ 0x08
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#define ATA_BMDEVSPEC_0 17
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#define ATA_BMSTAT_PORT 18
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#define ATA_BMSTAT_ACTIVE 0x01
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#define ATA_BMSTAT_ERROR 0x02
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#define ATA_BMSTAT_INTERRUPT 0x04
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#define ATA_BMSTAT_MASK 0x07
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#define ATA_BMSTAT_DMA_MASTER 0x20
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#define ATA_BMSTAT_DMA_SLAVE 0x40
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#define ATA_BMSTAT_DMA_SIMPLEX 0x80
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#define ATA_BMDEVSPEC_1 19
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#define ATA_BMDTP_PORT 20
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#define ATA_IDX_ADDR 21
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#define ATA_IDX_DATA 22
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#define ATA_MAX_RES 23
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/* misc defines */
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#define ATA_PRIMARY 0x1f0
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#define ATA_SECONDARY 0x170
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#define ATA_PC98_BANK 0x432
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#define ATA_IOSIZE 0x08
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#define ATA_PC98_IOSIZE 0x10
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#define ATA_CTLIOSIZE 0x01
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#define ATA_BMIOSIZE 0x08
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#define ATA_PC98_BANKIOSIZE 0x01
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#define ATA_IOADDR_RID 0
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#define ATA_CTLADDR_RID 1
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#define ATA_BMADDR_RID 0x20
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#define ATA_PC98_CTLADDR_RID 8
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#define ATA_PC98_BANKADDR_RID 9
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#define ATA_IRQ_RID 0
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#define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
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#define ATAPI_MAGIC_LSB 0x14
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#define ATAPI_MAGIC_MSB 0xeb
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#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN)
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#define ATAPI_P_WRITE (ATA_S_DRQ)
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#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD)
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#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN)
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#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN)
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#define ATAPI_P_ABORT 0
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#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
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#define ATA_OP_CONTINUES 0
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#define ATA_OP_FINISHED 1
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#define ATA_MAX_28BIT_LBA 268435455
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/* ATAPI request sense structure */
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struct atapi_sense {
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u_int8_t error_code :7; /* current or deferred errors */
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u_int8_t valid :1; /* follows ATAPI spec */
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u_int8_t segment; /* Segment number */
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u_int8_t sense_key :4; /* sense key */
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u_int8_t reserved2_4 :1; /* reserved */
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u_int8_t ili :1; /* incorrect length indicator */
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u_int8_t eom :1; /* end of medium */
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u_int8_t filemark :1; /* filemark */
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u_int32_t cmd_info __packed; /* cmd information */
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u_int8_t sense_length; /* additional sense len (n-7) */
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u_int32_t cmd_specific_info __packed; /* additional cmd spec info */
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u_int8_t asc; /* additional sense code */
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u_int8_t ascq; /* additional sense code qual */
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u_int8_t replaceable_unit_code; /* replaceable unit code */
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u_int8_t sk_specific :7; /* sense key specific */
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u_int8_t sksv :1; /* sense key specific info OK */
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u_int8_t sk_specific1; /* sense key specific */
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u_int8_t sk_specific2; /* sense key specific */
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};
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/* structure used for composite atomic operations */
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struct ata_composite {
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struct mtx lock; /* control lock */
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u_int32_t rd_needed; /* needed read subdisks */
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u_int32_t rd_done; /* done read subdisks */
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u_int32_t wr_needed; /* needed write subdisks */
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u_int32_t wr_depend; /* write depends on subdisks */
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u_int32_t wr_done; /* done write subdisks */
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struct ata_request *request[32]; /* size must match maps above */
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caddr_t data_1;
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caddr_t data_2;
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};
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/* structure used to queue an ATA/ATAPI request */
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struct ata_request {
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device_t dev; /* device handle */
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union {
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struct {
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u_int8_t command; /* command reg */
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u_int16_t feature; /* feature reg */
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u_int16_t count; /* count reg */
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u_int64_t lba; /* lba reg */
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} ata;
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struct {
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u_int8_t ccb[16]; /* ATAPI command block */
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struct atapi_sense sense_data; /* ATAPI request sense data */
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u_int8_t sense_key; /* ATAPI request sense key */
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u_int8_t sense_cmd; /* ATAPI saved command */
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} atapi;
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} u;
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u_int32_t bytecount; /* bytes to transfer */
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u_int32_t transfersize; /* bytes pr transfer */
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caddr_t data; /* pointer to data buf */
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int flags;
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#define ATA_R_CONTROL 0x00000001
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#define ATA_R_READ 0x00000002
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#define ATA_R_WRITE 0x00000004
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#define ATA_R_DMA 0x00000008
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#define ATA_R_ATAPI 0x00000010
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#define ATA_R_QUIET 0x00000020
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#define ATA_R_INTR_SEEN 0x00000040
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#define ATA_R_TIMEOUT 0x00000080
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#define ATA_R_ORDERED 0x00000100
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#define ATA_R_AT_HEAD 0x00000200
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#define ATA_R_REQUEUE 0x00000400
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#define ATA_R_THREAD 0x00000800
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#define ATA_R_DIRECT 0x00001000
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#define ATA_R_DEBUG 0x10000000
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u_int8_t status; /* ATA status */
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u_int8_t error; /* ATA error */
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u_int8_t dmastat; /* DMA status */
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u_int32_t donecount; /* bytes transferred */
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int result; /* result error code */
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void (*callback)(struct ata_request *request);
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struct sema done; /* request done sema */
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int retries; /* retry count */
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int timeout; /* timeout for this cmd */
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struct callout callout; /* callout management */
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struct task task; /* task management */
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struct bio *bio; /* bio for this request */
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int this; /* this request ID */
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struct ata_composite *composite; /* for composite atomic ops */
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void *driver; /* driver specific */
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TAILQ_ENTRY(ata_request) chain; /* list management */
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};
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/* define this for debugging request processing */
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#if 0
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#define ATA_DEBUG_RQ(request, string) \
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{ \
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if (request->flags & ATA_R_DEBUG) \
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device_printf(request->dev, "req=%p %s " string "\n", \
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request, ata_cmd2str(request)); \
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}
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#else
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#define ATA_DEBUG_RQ(request, string)
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#endif
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/* structure describing an ATA/ATAPI device */
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struct ata_device {
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device_t dev; /* device handle */
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int unit; /* physical unit */
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#define ATA_MASTER 0x00
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#define ATA_SLAVE 0x10
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struct ata_params param; /* ata param structure */
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int mode; /* current transfermode */
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u_int32_t max_iosize; /* max IO size */
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int cmd; /* last cmd executed */
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int flags;
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#define ATA_D_USE_CHS 0x0001
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#define ATA_D_MEDIA_CHANGED 0x0002
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#define ATA_D_ENC_PRESENT 0x0004
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};
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/* structure for holding DMA Physical Region Descriptors (PRD) entries */
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struct ata_dma_prdentry {
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u_int32_t addr;
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u_int32_t count;
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};
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/* structure used by the setprd function */
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struct ata_dmasetprd_args {
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void *dmatab;
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int error;
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};
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struct ata_channel {};
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/* structure holding DMA related information */
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struct ata_dma {
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bus_dma_tag_t dmatag; /* parent DMA tag */
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bus_dma_tag_t sg_tag; /* SG list DMA tag */
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bus_dmamap_t sg_map; /* SG list DMA map */
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void *sg; /* DMA transfer table */
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bus_addr_t sg_bus; /* bus address of dmatab */
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bus_dma_tag_t data_tag; /* data DMA tag */
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bus_dmamap_t data_map; /* data DMA map */
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bus_dma_tag_t work_tag; /* workspace DMA tag */
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bus_dmamap_t work_map; /* workspace DMA map */
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u_int8_t *work; /* workspace */
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bus_addr_t work_bus; /* bus address of dmatab */
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u_int32_t alignment; /* DMA engine alignment */
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u_int32_t boundary; /* DMA engine boundary */
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u_int32_t max_iosize; /* DMA engine max IO size */
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u_int32_t cur_iosize; /* DMA engine current IO size */
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int flags;
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#define ATA_DMA_READ 0x01 /* transaction is a read */
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#define ATA_DMA_LOADED 0x02 /* DMA tables etc loaded */
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#define ATA_DMA_ACTIVE 0x04 /* DMA transfer in progress */
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void (*alloc)(struct ata_channel *ch);
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void (*free)(struct ata_channel *ch);
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void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
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int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir);
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int (*unload)(struct ata_channel *ch);
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int (*start)(struct ata_channel *ch);
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int (*stop)(struct ata_channel *ch);
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};
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/* structure holding lowlevel functions */
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struct ata_lowlevel {
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int (*begin_transaction)(struct ata_request *request);
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int (*end_transaction)(struct ata_request *request);
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void (*reset)(struct ata_channel *ch);
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int (*command)(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
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};
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/* structure holding resources for an ATA channel */
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struct ata_resource {
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struct resource *res;
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int offset;
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};
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/* structure describing an ATA channel */
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struct ata_channel {
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device_t dev; /* device handle */
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int unit; /* physical channel */
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struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */
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struct resource *r_irq; /* interrupt of this channel */
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void *ih; /* interrupt handle */
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struct ata_lowlevel hw; /* lowlevel HW functions */
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struct ata_dma *dma; /* DMA data / functions */
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int flags; /* channel flags */
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#define ATA_NO_SLAVE 0x01
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#define ATA_USE_16BIT 0x02
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#define ATA_ATAPI_DMA_RO 0x04
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#define ATA_48BIT_ACTIVE 0x08
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int devices; /* what is present */
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#define ATA_ATA_MASTER 0x01
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#define ATA_ATA_SLAVE 0x02
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#define ATA_ATAPI_MASTER 0x04
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#define ATA_ATAPI_SLAVE 0x08
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struct mtx state_mtx; /* state lock */
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int state; /* ATA channel state */
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#define ATA_IDLE 0x0000
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#define ATA_ACTIVE 0x0001
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#define ATA_STALL_QUEUE 0x0002
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#define ATA_TIMEOUT 0x0004
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struct mtx queue_mtx; /* queue lock */
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TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */
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struct ata_request *freezepoint; /* composite freezepoint */
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struct ata_request *running; /* currently running request */
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};
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/* disk bay/enclosure related */
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#define ATA_LED_OFF 0x00
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#define ATA_LED_RED 0x01
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#define ATA_LED_GREEN 0x02
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#define ATA_LED_ORANGE 0x03
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#define ATA_LED_MASK 0x03
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/* externs */
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extern int (*ata_ioctl_func)(struct ata_cmd *iocmd);
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extern devclass_t ata_devclass;
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extern int ata_wc;
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/* public prototypes */
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/* ata-all.c: */
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int ata_probe(device_t dev);
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int ata_attach(device_t dev);
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int ata_detach(device_t dev);
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int ata_reinit(device_t dev);
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int ata_suspend(device_t dev);
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int ata_resume(device_t dev);
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void ata_default_registers(struct ata_channel *ch);
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void ata_udelay(int interval);
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char *ata_mode2str(int mode);
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int ata_pmode(struct ata_params *ap);
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int ata_wmode(struct ata_params *ap);
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int ata_umode(struct ata_params *ap);
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int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode);
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/* ata-queue.c: */
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int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count);
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int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout);
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void ata_queue_request(struct ata_request *request);
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void ata_start(device_t dev);
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void ata_finish(struct ata_request *request);
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void ata_catch_inflight(struct ata_channel *ch);
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void ata_fail_requests(struct ata_channel *ch, device_t dev);
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char *ata_cmd2str(struct ata_request *request);
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/* ata-lowlevel.c: */
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void ata_generic_hw(struct ata_channel *ch);
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int ata_generic_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature);
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int ata_getparam(device_t parent, struct ata_device *atadev, u_int8_t command);
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/* macros for alloc/free of struct ata_request */
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extern uma_zone_t ata_request_zone;
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#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO)
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#define ata_free_request(request) uma_zfree(ata_request_zone, request)
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/* macros for alloc/free of struct ata_composite */
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extern uma_zone_t ata_composite_zone;
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#define ata_alloc_composite() uma_zalloc(ata_composite_zone, M_NOWAIT | M_ZERO)
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#define ata_free_composite(composite) uma_zfree(ata_composite_zone, composite)
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MALLOC_DECLARE(M_ATA);
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|
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/* misc newbus defines */
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#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
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|
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/* macros to hide busspace uglyness */
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#define ATA_INB(res, offset) \
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bus_space_read_1(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset))
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#define ATA_INW(res, offset) \
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bus_space_read_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset))
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#define ATA_INL(res, offset) \
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bus_space_read_4(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset))
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#define ATA_INSW(res, offset, addr, count) \
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bus_space_read_multi_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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(offset), (addr), (count))
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#define ATA_INSW_STRM(res, offset, addr, count) \
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bus_space_read_multi_stream_2(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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(offset), (addr), (count))
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#define ATA_INSL(res, offset, addr, count) \
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bus_space_read_multi_4(rman_get_bustag((res)), \
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rman_get_bushandle((res)), \
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|
(offset), (addr), (count))
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#define ATA_INSL_STRM(res, offset, addr, count) \
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bus_space_read_multi_stream_4(rman_get_bustag((res)), \
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|
rman_get_bushandle((res)), \
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|
(offset), (addr), (count))
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#define ATA_OUTB(res, offset, value) \
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bus_space_write_1(rman_get_bustag((res)), \
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rman_get_bushandle((res)), (offset), (value))
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#define ATA_OUTW(res, offset, value) \
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bus_space_write_2(rman_get_bustag((res)), \
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|
rman_get_bushandle((res)), (offset), (value))
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#define ATA_OUTL(res, offset, value) \
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bus_space_write_4(rman_get_bustag((res)), \
|
|
rman_get_bushandle((res)), (offset), (value))
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#define ATA_OUTSW(res, offset, addr, count) \
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|
bus_space_write_multi_2(rman_get_bustag((res)), \
|
|
rman_get_bushandle((res)), \
|
|
(offset), (addr), (count))
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#define ATA_OUTSW_STRM(res, offset, addr, count) \
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|
bus_space_write_multi_stream_2(rman_get_bustag((res)), \
|
|
rman_get_bushandle((res)), \
|
|
(offset), (addr), (count))
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|
#define ATA_OUTSL(res, offset, addr, count) \
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|
bus_space_write_multi_4(rman_get_bustag((res)), \
|
|
rman_get_bushandle((res)), \
|
|
(offset), (addr), (count))
|
|
#define ATA_OUTSL_STRM(res, offset, addr, count) \
|
|
bus_space_write_multi_stream_4(rman_get_bustag((res)), \
|
|
rman_get_bushandle((res)), \
|
|
(offset), (addr), (count))
|
|
|
|
#define ATA_IDX_INB(ch, idx) \
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|
ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset)
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|
|
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#define ATA_IDX_INW(ch, idx) \
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|
ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset)
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|
|
|
#define ATA_IDX_INL(ch, idx) \
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|
ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset)
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|
|
|
#define ATA_IDX_INSW(ch, idx, addr, count) \
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|
ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
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|
|
|
#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \
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|
ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|
|
|
|
#define ATA_IDX_INSL(ch, idx, addr, count) \
|
|
ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|
|
|
|
#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \
|
|
ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|
|
|
|
#define ATA_IDX_OUTB(ch, idx, value) \
|
|
ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value)
|
|
|
|
#define ATA_IDX_OUTW(ch, idx, value) \
|
|
ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value)
|
|
|
|
#define ATA_IDX_OUTL(ch, idx, value) \
|
|
ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value)
|
|
|
|
#define ATA_IDX_OUTSW(ch, idx, addr, count) \
|
|
ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|
|
|
|
#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \
|
|
ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|
|
|
|
#define ATA_IDX_OUTSL(ch, idx, addr, count) \
|
|
ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|
|
|
|
#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \
|
|
ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count)
|