b3eb962304
almost works properly. Unfortunately, there is no way to flush the rx fifo without resetting the channel, which also flushes the tx fifo. We avoid resetting even when both fifos need to be flushed, since resetting seems to cause the rx to lose sync if it is done while data is arriving. Reminded by: NIST-PCTS |
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.. | ||
apm | ||
bios | ||
boot | ||
conf | ||
eisa | ||
i386 | ||
ibcs2 | ||
include | ||
isa | ||
linux | ||
pci | ||
Makefile |