04d0965e76
These are going to be much more efficient on low end embedded systems but unfortunately they make it .. less convenient to implement correct bus barriers and debugging. They also didn't implement the register serialisation workaround required for Owl (AR5416.) So, just remove them for now. Later on I'll just inline the routines from ah_osdep.c.
150 lines
5.2 KiB
C
150 lines
5.2 KiB
C
/*-
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AH_OSDEP_H_
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#define _ATH_AH_OSDEP_H_
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/*
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* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/linker_set.h>
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#include <machine/bus.h>
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/*
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* Bus i/o type definitions.
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*/
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typedef void *HAL_SOFTC;
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typedef bus_space_tag_t HAL_BUS_TAG;
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typedef bus_space_handle_t HAL_BUS_HANDLE;
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/*
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* Although the underlying hardware may support 64 bit DMA, the
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* current Atheros hardware only supports 32 bit addressing.
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*/
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typedef uint32_t HAL_DMA_ADDR;
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/*
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* Linker set writearounds for chip and RF backend registration.
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*/
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#define OS_DATA_SET(set, item) DATA_SET(set, item)
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#define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype)
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#define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set)
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/*
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* Delay n microseconds.
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*/
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#define OS_DELAY(_n) DELAY(_n)
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#define OS_INLINE __inline
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#define OS_MEMZERO(_a, _n) bzero((_a), (_n))
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#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n)
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#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l))
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#define abs(_a) __builtin_abs(_a)
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struct ath_hal;
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/*
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* The hardware registers are native little-endian byte order.
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* Big-endian hosts are handled by enabling hardware byte-swap
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* of register reads and writes at reset. But the PCI clock
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* domain registers are not byte swapped! Thus, on big-endian
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* platforms we have to explicitly byte-swap those registers.
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* OS_REG_UNSWAPPED identifies the registers that need special handling.
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*
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* This is not currently used by the FreeBSD HAL osdep code; the HAL
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* currently does not configure hardware byteswapping for register space
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* accesses and instead does it through the FreeBSD bus space code.
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*/
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_UNSWAPPED(_reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) || \
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((_reg) >= 0x7000 && (_reg) < 0x8000))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_UNSWAPPED(_reg) (0)
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#endif /* _BYTE_ORDER */
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/*
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* For USB/SDIO support (where access latencies are quite high);
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* some write accesses may be buffered and then flushed when
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* either a read is done, or an explicit flush is done.
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*
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* These are simply placeholders for now.
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*/
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#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \
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do { } while (0)
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#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \
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do { } while (0)
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#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \
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do { } while (0)
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/*
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* Read and write barriers. Some platforms require more strongly ordered
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* operations and unfortunately most of the HAL is written assuming everything
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* is either an x86 or the bus layer will do the barriers for you.
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*
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* Read barriers should occur before each read, and write barriers
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* occur after each write.
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*
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* Later on for SDIO/USB parts we will methodize this and make them no-ops;
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* register accesses will go via USB commands.
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*/
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#define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ
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#define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE
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#define OS_BUS_BARRIER_RW \
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(BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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#define OS_BUS_BARRIER(_ah, _start, _len, _t) \
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bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t))
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#define OS_BUS_BARRIER_REG(_ah, _reg, _t) \
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OS_BUS_BARRIER((_ah), (_reg), 4, (_t))
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/*
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* Register read/write operations are handled through
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* platform-dependent routines.
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*/
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#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
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extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
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extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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#ifdef AH_DEBUG_ALQ
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extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
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#else
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#define OS_MARK(_ah, _id, _v)
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#endif
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#endif /* _ATH_AH_OSDEP_H_ */
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