97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/* $FreeBSD$ */
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/* $NecBSD: bshwvar.h,v 1.3.14.3 2001/06/21 04:07:37 honda Exp $ */
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/* $NetBSD$ */
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/*
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* [NetBSD for NEC PC-98 series]
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* Copyright (c) 1994, 1995, 1996, 1997, 1998
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* NetBSD/pc98 porting staff. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BSHWVAR_H_
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#define _BSHWVAR_H_
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/*
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* bshwvar.h
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* NEC 55 compatible board specific definitions
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*/
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#define BSHW_DEFAULT_CHIPCLK 20 /* 20MHz */
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#define BSHW_DEFAULT_HOSTID 7
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struct bshw {
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#define BSHW_SYNC_RELOAD 0x01
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#define BSHW_SMFIFO 0x02
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#define BSHW_DOUBLE_DMACHAN 0x04
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u_int hw_flags;
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u_int hw_sregaddr;
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int ((*hw_dma_init)(struct ct_softc *));
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void ((*hw_dma_start)(struct ct_softc *));
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void ((*hw_dma_stop)(struct ct_softc *));
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};
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struct bshw_softc {
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int sc_hostid;
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int sc_irq; /* irq */
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int sc_drq; /* drq */
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/* dma transfer */
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u_int8_t *sc_segaddr;
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u_int8_t *sc_bufp;
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int sc_seglen;
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u_int sc_sdatalen; /* SMIT */
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u_int sc_edatalen; /* SMIT */
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/* private bounce */
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u_int8_t *sc_bounce_phys;
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u_int8_t *sc_bounce_addr;
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u_int sc_bounce_size;
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bus_addr_t sc_minphys;
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/* io control */
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#define BSHW_READ_INTERRUPT_DRIVEN 0x0001
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#define BSHW_WRITE_INTERRUPT_DRIVEN 0x0002
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#define BSHW_DMA_BLOCK 0x0010
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#define BSHW_SMIT_BLOCK 0x0020
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u_int sc_io_control;
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/* hardware */
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struct bshw *sc_hw;
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void ((*sc_dmasync_before))(struct ct_softc *);
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void ((*sc_dmasync_after))(struct ct_softc *);
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};
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void bshw_synch_setup(struct ct_softc *, struct targ_info *);
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void bshw_bus_reset(struct ct_softc *);
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int bshw_read_settings(struct ct_bus_access_handle *, struct bshw_softc *);
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int bshw_smit_xfer_start(struct ct_softc *);
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void bshw_smit_xfer_stop(struct ct_softc *);
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int bshw_dma_xfer_start(struct ct_softc *);
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void bshw_dma_xfer_stop(struct ct_softc *);
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extern struct dvcfg_hwsel bshw_hwsel;
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#endif /* !_BSHWVAR_H_ */
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