177 lines
6.4 KiB
C
177 lines
6.4 KiB
C
/*
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* Copyright 1991-1998 by Open Software Foundation, Inc.
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* All Rights Reserved
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies and
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* that both the copyright notice and this permission notice appear in
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* supporting documentation.
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*
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* OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
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* NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
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* WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Copyright 2003 by Peter Grehan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* BMAC resource indices
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*/
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#define BM_MAIN_REGISTERS 0
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#define BM_TXDMA_REGISTERS 1
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#define BM_RXDMA_REGISTERS 2
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#define BM_MAIN_INTERRUPT 0
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#define BM_TXDMA_INTERRUPT 1
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#define BM_RXDMA_INTERRUPT 2
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/*
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* BMAC/BMAC+ register offsets
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*/
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#define BM_TX_IFC 0x0000 /* interface control */
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#define BM_TXFIFO_CSR 0x0100 /* TX FIFO control/status */
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#define BM_TX_THRESH 0x0110 /* TX threshold */
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#define BM_RXFIFO_CSR 0x0120 /* receive FIFO control/status */
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#define BM_MEMADD 0x0130 /* unused */
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#define BM_MEMDATA_HI 0x0140 /* unused */
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#define BM_MEMDATA_LO 0x0150 /* unused */
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#define BM_XCVR 0x0160 /* transceiver control register */
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#define BM_CHIPID 0x0170 /* chip ID */
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#define BM_MII_CSR 0x0180 /* MII control register */
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#define BM_SROM_CSR 0x0190 /* unused, OFW provides enet addr */
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#define BM_TX_PTR 0x01A0 /* unused */
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#define BM_RX_PTR 0x01B0 /* unused */
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#define BM_STATUS 0x01C0 /* status register */
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#define BM_INTR_DISABLE 0x0200 /* interrupt control register */
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#define BM_TX_RESET 0x0420 /* TX reset */
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#define BM_TX_CONFIG 0x0430 /* TX config */
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#define BM_IPG1 0x0440 /* inter-packet gap hi */
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#define BM_IPG2 0x0450 /* inter-packet gap lo */
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#define BM_TX_ALIMIT 0x0460 /* TX attempt limit */
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#define BM_TX_STIME 0x0470 /* TX slot time */
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#define BM_TX_PASIZE 0x0480 /* TX preamble size */
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#define BM_TX_PAPAT 0x0490 /* TX preamble pattern */
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#define BM_TX_SFD 0x04A0 /* TX start-frame delimiter */
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#define BM_JAMSIZE 0x04B0 /* collision jam size */
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#define BM_TX_MAXLEN 0x04C0 /* max TX packet length */
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#define BM_TX_MINLEN 0x04D0 /* min TX packet length */
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#define BM_TX_PEAKCNT 0x04E0 /* TX peak attempts count */
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#define BM_TX_DCNT 0x04F0 /* TX defer timer */
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#define BM_TX_NCCNT 0x0500 /* TX normal collision cnt */
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#define BM_TX_FCCNT 0x0510 /* TX first collision cnt */
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#define BM_TX_EXCNT 0x0520 /* TX excess collision cnt */
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#define BM_TX_LTCNT 0x0530 /* TX late collision cnt */
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#define BM_TX_RANDSEED 0x0540 /* TX random seed */
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#define BM_TXSM 0x0550 /* TX state machine */
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#define BM_RX_RESET 0x0620 /* RX reset */
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#define BM_RX_CONFIG 0x0630 /* RX config */
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#define BM_RX_MAXLEN 0x0640 /* max RX packet length */
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#define BM_RX_MINLEN 0x0650 /* min RX packet length */
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#define BM_MACADDR2 0x0660 /* MAC address */
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#define BM_MACADDR1 0x0670
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#define BM_MACADDR0 0x0680
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#define BM_RX_FRCNT 0x0690 /* RX frame count */
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#define BM_RX_LECNT 0x06A0 /* RX too-long frame count */
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#define BM_RX_AECNT 0x06B0 /* RX misaligned frame count */
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#define BM_RX_FECNT 0x06C0 /* RX CRC error count */
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#define BM_RXSM 0x06D0 /* RX state machine */
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#define BM_RXCV 0x06E0 /* RX code violations */
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#define BM_HASHTAB3 0x0700 /* Address hash table */
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#define BM_HASHTAB2 0x0710
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#define BM_HASHTAB1 0x0720
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#define BM_HASHTAB0 0x0730
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#define BM_AFILTER2 0x0740 /* Address filter */
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#define BM_AFILTER1 0x0750
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#define BM_AFILTER0 0x0760
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#define BM_AFILTER_MASK 0x0770
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/*
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* MII control register bits
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*/
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#define BM_MII_CLK 0x0001 /* MDIO clock */
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#define BM_MII_DATAOUT 0x0002 /* MDIO data out */
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#define BM_MII_OENABLE 0x0004 /* MDIO output enable */
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#define BM_MII_DATAIN 0x0008 /* MDIO data in */
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/*
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* MII constants
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*/
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#define BM_MII_STARTDELIM 0x01
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#define BM_MII_READOP 0x02
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#define BM_MII_WRITEOP 0x01
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#define BM_MII_TURNAROUND 0x02
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/*
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* Various flags
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*/
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#define BM_ENABLE 0x0001
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#define BM_CRC_ENABLE 0x0100
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#define BM_HASH_FILTER_ENABLE 0x0200
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#define BM_REJECT_OWN_PKTS 0x0800
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#define BM_PROMISC 0x0040
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#define BM_TX_FULLDPX 0x0200
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#define BM_TX_IGNORECOLL 0x0040
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#define BM_INTR_PKT_RX 0x0001
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#define BM_INTR_PKT_TX 0x0100
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#define BM_INTR_TX_UNDERRUN 0x0200
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#define BM_INTR_NORMAL ~(BM_INTR_PKT_TX | BM_INTR_TX_UNDERRUN)
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#define BM_INTR_NONE 0xffff
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_write_4(sc->sc_memr, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_write_2(sc->sc_memr, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_write_1(sc->sc_memr, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_read_4(sc->sc_memr, reg)
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#define CSR_READ_2(sc, reg) \
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bus_read_2(sc->sc_memr, reg)
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#define CSR_READ_1(sc, reg) \
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bus_read_1(sc->sc_memr, reg)
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