b837332d0a
related issues. Moving the TX locking under one lock made things easier to progress on but it had one important side-effect - it increased the latency when handling CABQ setup when sending beacons. This commit introduces a bunch of new changes and a few unrelated changs that are just easier to lump in here. The aim is to have the CABQ locking separate from other locking. The CABQ transmit path in the beacon process thus doesn't have to grab the general TX lock, reducing lock contention/latency and making it more likely that we'll make the beacon TX timing. The second half of this commit is the CABQ related setup changes needed for sane looking EDMA CABQ support. Right now the EDMA TX code naively assumes that only one frame (MPDU or A-MPDU) is being pushed into each FIFO slot. For the CABQ this isn't true - a whole list of frames is being pushed in - and thus CABQ handling breaks very quickly. The aim here is to setup the CABQ list and then push _that list_ to the hardware for transmission. I can then extend the EDMA TX code to stamp that list as being "one" FIFO entry (likely by tagging the last buffer in that list as "FIFO END") so the EDMA TX completion code correctly tracks things. Major: * Migrate the per-TXQ add/removal locking back to per-TXQ, rather than a single lock. * Leave the software queue side of things under the ATH_TX_LOCK lock, (continuing) to serialise things as they are. * Add a new function which is called whenever there's a beacon miss, to print out some debugging. This is primarily designed to help me figure out if the beacon miss events are due to a noisy environment, issues with the PHY/MAC, or other. * Move the CABQ setup/enable to occur _after_ all the VAPs have been looked at. This means that for multiple VAPS in bursted mode, the CABQ gets primed once all VAPs are checked, rather than being primed on the first VAP and then having frames appended after this. Minor: * Add a (disabled) twiddle to let me enable/disable cabq traffic. It's primarily there to let me easily debug what's going on with beacon and CABQ setup/traffic; there's some DMA engine hangs which I'm finally trying to trace down. * Clear bf_next when flushing frames; it should quieten some warnings that show up when a node goes away. Tested: * AR9280, STA/hostap, up to 4 vaps (staggered) * AR5416, STA/hostap, up to 4 vaps (staggered) TODO: * (Lots) more AR9380 and later testing, as I may have missed something here. * Leverage this to fix CABQ hanling for AR9380 and later chips. * Force bursted beaconing on the chips that default to staggered beacons and ensure the CABQ stuff is all sane (eg, the MORE bits that aren't being correctly set when chaining descriptors.)
149 lines
5.2 KiB
C
149 lines
5.2 KiB
C
/*-
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef __IF_ATH_MISC_H__
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#define __IF_ATH_MISC_H__
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/*
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* This is where definitions for "public things" in if_ath.c
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* will go for the time being.
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*
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* Anything in here should eventually be moved out of if_ath.c
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* and into something else.
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*/
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/* unaligned little endian access */
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#define LE_READ_2(p) \
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((u_int16_t) \
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((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
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#define LE_READ_4(p) \
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((u_int32_t) \
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((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
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(((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
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extern int ath_rxbuf;
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extern int ath_txbuf;
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extern int ath_txbuf_mgmt;
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extern int ath_tx_findrix(const struct ath_softc *sc, uint8_t rate);
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extern struct ath_buf * ath_getbuf(struct ath_softc *sc,
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ath_buf_type_t btype);
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extern struct ath_buf * _ath_getbuf_locked(struct ath_softc *sc,
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ath_buf_type_t btype);
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extern struct ath_buf * ath_buf_clone(struct ath_softc *sc,
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const struct ath_buf *bf);
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/* XXX change this to NULL the buffer pointer? */
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extern void ath_freebuf(struct ath_softc *sc, struct ath_buf *bf);
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extern void ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf);
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extern void ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf);
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extern int ath_reset(struct ifnet *, ATH_RESET_TYPE);
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extern void ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf,
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int fail);
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extern void ath_tx_update_ratectrl(struct ath_softc *sc,
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struct ieee80211_node *ni, struct ath_rc_series *rc,
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struct ath_tx_status *ts, int frmlen, int nframes, int nbad);
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extern int ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask,
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uint32_t *hangs);
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extern void ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf,
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int status);
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extern void ath_txqmove(struct ath_txq *dst, struct ath_txq *src);
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extern void ath_mode_init(struct ath_softc *sc);
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extern void ath_setdefantenna(struct ath_softc *sc, u_int antenna);
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extern void ath_setslottime(struct ath_softc *sc);
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extern int ath_descdma_alloc_desc(struct ath_softc *sc,
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struct ath_descdma *dd, ath_bufhead *head, const char *name,
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int ds_size, int ndesc);
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extern int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
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ath_bufhead *head, const char *name, int ds_size, int nbuf,
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int ndesc);
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extern int ath_descdma_setup_rx_edma(struct ath_softc *sc,
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struct ath_descdma *dd, ath_bufhead *head, const char *name,
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int nbuf, int desclen);
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extern void ath_descdma_cleanup(struct ath_softc *sc,
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struct ath_descdma *dd, ath_bufhead *head);
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extern void ath_legacy_attach_comp_func(struct ath_softc *sc);
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extern void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq);
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extern void ath_legacy_tx_drain(struct ath_softc *sc,
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ATH_RESET_TYPE reset_type);
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extern void ath_tx_process_buf_completion(struct ath_softc *sc,
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struct ath_txq *txq, struct ath_tx_status *ts, struct ath_buf *bf);
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extern int ath_stoptxdma(struct ath_softc *sc);
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extern void ath_tx_update_tim(struct ath_softc *sc,
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struct ieee80211_node *ni, int enable);
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/*
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* This is only here so that the RX proc function can call it.
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* It's very likely that the "start TX after RX" call should be
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* done via something in if_ath.c, moving "rx tasklet" into
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* if_ath.c and do the ath_start() call there. Once that's done,
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* we can kill this.
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*/
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extern void ath_start(struct ifnet *ifp);
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extern void ath_start_task(void *arg, int npending);
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/*
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* Kick the frame TX task.
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*/
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static inline void
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ath_tx_kick(struct ath_softc *sc)
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{
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ATH_TX_LOCK(sc);
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ath_start(sc->sc_ifp);
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ATH_TX_UNLOCK(sc);
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}
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/*
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* Kick the software TX queue task.
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*/
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static inline void
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ath_tx_swq_kick(struct ath_softc *sc)
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{
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taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
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}
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#endif
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