34c15db9cd
use PAE format for the page tables, but does not incur other consequences of the full PAE config. In particular, vm_paddr_t and bus_addr_t are left 32bit, and max supported memory is still limited by 4GB. The option allows to have nx permissions for memory mappings on i386 kernel, while keeping the usual i386 KBI and avoiding the kernel data sizing problems typical for the PAE config. Intel documented that the PAE format for page tables is available starting with the Pentium Pro, but it is possible that the plain Pentium CPUs have the required support (Appendix H). The goal is to enable the option and non-exec mappings on i386 for the GENERIC kernel. Anybody wanting a useful system on 486, have to reconfigure the modern i386 kernel anyway. Discussed with: alc, jhb Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
161 lines
5.0 KiB
C
161 lines
5.0 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)param.h 5.8 (Berkeley) 6/28/91
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* $FreeBSD$
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*/
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#ifndef _I386_INCLUDE_PARAM_H_
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#define _I386_INCLUDE_PARAM_H_
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#include <machine/_align.h>
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/*
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* Machine dependent constants for Intel 386.
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*/
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#define __HAVE_ACPI
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#define __HAVE_PIR
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#define __PCI_REROUTE_INTERRUPT
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#ifndef MACHINE
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#define MACHINE "i386"
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#endif
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#ifndef MACHINE_ARCH
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#define MACHINE_ARCH "i386"
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#endif
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#define MID_MACHINE MID_I386
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#if defined(SMP) || defined(KLD_MODULE)
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#ifndef MAXCPU
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#define MAXCPU 32
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#endif
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#else
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#define MAXCPU 1
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#endif /* SMP || KLD_MODULE */
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#ifndef MAXMEMDOM
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#define MAXMEMDOM 1
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#endif
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#define ALIGNBYTES _ALIGNBYTES
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#define ALIGN(p) _ALIGN(p)
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/*
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* ALIGNED_POINTER is a boolean macro that checks whether an address
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* is valid to fetch data elements of type t from on this architecture.
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* This does not reflect the optimal alignment, just the possibility
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* (within reasonable limits).
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*/
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#define ALIGNED_POINTER(p, t) 1
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/*
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* CACHE_LINE_SIZE is the compile-time maximum cache line size for an
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* architecture. It should be used with appropriate caution.
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*/
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#define CACHE_LINE_SHIFT 7
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
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#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
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#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
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#define PAGE_MASK (PAGE_SIZE-1)
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#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
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#if defined(PAE) || defined(PAE_TABLES)
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#define NPGPTD 4
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#define PDRSHIFT 21 /* LOG2(NBPDR) */
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#define NPGPTD_SHIFT 9
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#else
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#define NPGPTD 1
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#define PDRSHIFT 22 /* LOG2(NBPDR) */
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#define NPGPTD_SHIFT 10
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#endif
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#define NBPTD (NPGPTD<<PAGE_SHIFT)
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#define NPDEPTD (NBPTD/(sizeof (pd_entry_t)))
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#define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
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#define NBPDR (1<<PDRSHIFT) /* bytes/page dir */
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#define PDRMASK (NBPDR-1)
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#define MAXPAGESIZES 2 /* maximum number of supported page sizes */
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#define IOPAGES 2 /* pages of i/o permission bitmap */
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#ifndef KSTACK_PAGES
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#define KSTACK_PAGES 2 /* Includes pcb! */
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#endif
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#define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
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/*
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* Ceiling on amount of swblock kva space, can be changed via
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* the kern.maxswzone /boot/loader.conf variable.
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*
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* 276 is sizeof(struct swblock), but we do not always have a definition
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* in scope for struct swblock, so we have to hardcode it. Each struct
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* swblock holds metadata for 32 pages, so in theory, this is enough for
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* 16 GB of swap. In practice, however, the usable amount is considerably
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* lower due to fragmentation.
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*/
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#ifndef VM_SWZONE_SIZE_MAX
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#define VM_SWZONE_SIZE_MAX (276 * 128 * 1024)
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#endif
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/*
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* Ceiling on size of buffer cache (really only effects write queueing,
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* the VM page cache is not effected), can be changed via
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* the kern.maxbcache /boot/loader.conf variable.
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*
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* The value is equal to the size of the auto-tuned buffer map for
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* the machine with 4GB of RAM, see vfs_bio.c:kern_vfs_bio_buffer_alloc().
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*/
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#ifndef VM_BCACHE_SIZE_MAX
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#define VM_BCACHE_SIZE_MAX (7224 * 16 * 1024)
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#endif
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/*
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* Mach derived conversion macros
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*/
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#define trunc_page(x) ((x) & ~PAGE_MASK)
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#define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK)
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#define trunc_4mpage(x) ((x) & ~PDRMASK)
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#define round_4mpage(x) ((((x)) + PDRMASK) & ~PDRMASK)
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#define atop(x) ((x) >> PAGE_SHIFT)
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#define ptoa(x) ((x) << PAGE_SHIFT)
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#define i386_btop(x) ((x) >> PAGE_SHIFT)
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#define i386_ptob(x) ((x) << PAGE_SHIFT)
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#define pgtok(x) ((x) * (PAGE_SIZE / 1024))
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#endif /* !_I386_INCLUDE_PARAM_H_ */
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