Sean Bruno e31b1dc894 Update Features2 to display SDBG capability of processor. This is ... showing up on Haswell-class CPUs From the Intel SDM, "Table 3-20. Feature Information Returned in the ECX Register" 11 | SDBG | A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug. Submitted by: jiashiun@gmail.com Reviewed by: jhb neel MFC after: 2 weeks		2015-01-08 16:50:35 +00:00
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_align.h
_inttypes.h
_limits.h
_stdint.h
_types.h
acpica_machdep.h
apicreg.h
apicvar.h
apm_bios.h
bus.h
busdma_impl.h
dump.h	Factor out duplicated code from dumpsys() on each architecture into generic	2015-01-07 01:01:39 +00:00
elf.h
endian.h
fdt.h
float.h
fpu.h	Improve support for XSAVE with debuggers.	2014-11-21 20:53:17 +00:00
frame.h
init.h
legacyvar.h
mca.h
mptable.h
ofw_machdep.h
pci_cfgreg.h
psl.h
ptrace.h	Improve support for XSAVE with debuggers.	2014-11-21 20:53:17 +00:00
reg.h
segments.h
setjmp.h
sigframe.h
signal.h
specialreg.h	Update Features2 to display SDBG capability of processor. This is	2015-01-08 16:50:35 +00:00
stdarg.h
sysarch.h
trap.h
ucontext.h
vdso.h
vmware.h	Rework virtual machine hypervisor detection.	2014-10-28 19:17:44 +00:00