ddcbd7a1c9
The QUICC engine is found on various Freescale parts including MPC85xx, and provides multiple generic time-division serial channel resources, which are in turn muxed/demuxed by the Serial Communications Controller (SCC). Along with core QUICC/SCC functionality a uart(4)-compliant device driver is provided which allows for serial ports over QUICC/SCC. Approved by: cognet (mentor) Obtained from: Juniper MFp4: e500
74 lines
2.6 KiB
C
74 lines
2.6 KiB
C
/*-
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* Copyright 2006 by Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_QUICC_BFE_H_
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#define _DEV_QUICC_BFE_H_
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struct quicc_device;
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struct quicc_softc {
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device_t sc_dev;
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struct resource *sc_rres; /* Register resource. */
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int sc_rrid;
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int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
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struct resource *sc_ires; /* Interrupt resource. */
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void *sc_icookie;
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int sc_irid;
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struct rman sc_rman;
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struct quicc_device *sc_device;
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u_int sc_clock;
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int sc_fastintr:1;
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int sc_leaving:1;
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int sc_polled:1;
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};
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extern devclass_t quicc_devclass;
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extern char quicc_driver_name[];
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int quicc_bfe_attach(device_t);
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int quicc_bfe_detach(device_t);
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int quicc_bfe_probe(device_t, u_int);
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struct resource *quicc_bus_alloc_resource(device_t, device_t, int, int *,
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u_long, u_long, u_long, u_int);
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int quicc_bus_get_resource(device_t, device_t, int, int, u_long *, u_long *);
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int quicc_bus_read_ivar(device_t, device_t, int, uintptr_t *);
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int quicc_bus_release_resource(device_t, device_t, int, int, struct resource *);
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int quicc_bus_setup_intr(device_t, device_t, struct resource *, int,
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driver_filter_t *, void (*)(void *), void *, void **);
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int quicc_bus_teardown_intr(device_t, device_t, struct resource *, void *);
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#endif /* _DEV_QUICC_BFE_H_ */
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