438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* CORTEX-I Frame Grabber driver V1.0
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*
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* Copyright (C) 1994, Paul S. LaFollette, Jr. This software may be used,
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* modified, copied, distributed, and sold, in both source and binary form
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* provided that the above copyright and these terms are retained. Under
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* no circumstances is the author responsible for the proper functioning
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* of this software, nor does the author assume any responsibility
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* for damages incurred with its use.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Device Driver for CORTEX-I Frame Grabber
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* Made by ImageNation Corporation
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* 1200 N.E. Keyues Road
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* Vancouver, WA 98684 (206) 944-9131
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* (I have no ties to this company, just thought you might want
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* to know how to get in touch with them.)
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*
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* In order to understand this device, you really need to consult the
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* manual which ImageNation provides when you buy the board. (And
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* what a pleasure it is to buy something for a PC and actually get
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* programming information along with it.) I will limit myself here to
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* a few comments which are specific to this driver. See also the file
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* ctxreg.h for definitions of registers and control bits.
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*
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* 1. Although the hardware supports low resolution (256 x 256)
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* acqusition and display, I have not implemented access to
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* these modes in this driver. There are some fairly quirky
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* aspects to the way this board works in low resolution mode,
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* and I don't want to deal with them. Maybe later.
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*
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* 2. Choosing the base address for the video memory: This is set
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* using a combination of hardware and software, using the left
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* most dip switch on the board, and the AB_SELECT bit of control
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* port 1, according to the chart below:
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*
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* Left DIP switch || DOWN | UP |
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* =================================================
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* AB_SELECT = 0 || 0xA0000 | 0xB0000 |
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* -------------------------------------------------
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* AB_SELECT = 1 || 0xD0000 | 0xE0000 |
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* ------------------------------------------------
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*
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* When the RAM_ENABLE bit of control port 1 is clear (0), the
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* video ram is disconnected from the computer bus. This makes
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* it possible, in principle, to share memory space with other
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* devices (such as VGA) which can also disconnect themselves
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* from the bus. It also means that multiple CORTEX-I boards
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* can share the same video memory space. Disconnecting from the
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* bus does not affect the video display of the video ram contents,
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* so that one needs only set the RAM_ENABLE bit when actually
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* reading or writing to memory. The cost of this is low,
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* the benefits to me are great (I need more than one board
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* in my machine, and 0xE0000 is the only address choice that
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* doesn't conflict with anything) so I adopt this strategy here.
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*
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* XXX-Note... this driver has only been tested for the
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* XXX base = 0xE0000 case!
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*
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* 3) There is a deficiency in the documentation from ImageNation, I
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* think. In order to successfully load the lookup table, it is
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* necessary to clear SEE_STORED_VIDEO in control port 0 as well as
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* setting LUT_LOAD_ENABLE in control port 1.
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*
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* 4) This driver accesses video memory through read or write operations.
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* Other functionality is provided through ioctl's, manifest
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* constants for which are defined in ioctl_ctx.h. The ioctl's
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* include:
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* CTX_LIVE Display live video
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* CTX_GRAB Grab a frame of video data
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* CTX_H_ORGANIZE Set things up so that sequential read
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* operations access horizontal lines of
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* pixels.
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* CTX_V_ORGANIZE Set things up so that sequential read
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* operations access vertical lines of
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* pixels.
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* CTX_SET_LUT Set the lookup table from an array
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* of 256 unsigned chars passed as the
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* third parameter to ioctl.
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* CTX_GET_LUT Return the current lookup table to
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* the application as an array of 256
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* unsigned chars. Again the third
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* parameter to the ioctl call.
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*
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* Thus,
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* ioctl(fi, CTX_H_ORGANIZE, 0);
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* lseek(fi, y*512, SEEK_SET);
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* read(fi, buffer, 512);
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*
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* will fill buffer with 512 pixels (unsigned chars) which represent
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* the y-th horizontal line of the image.
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* Similarly,
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* ioctl(fi, CTX_V_ORGANIZE, 0:
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* lseek(fi, x*512+y, SEEK_SET);
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* read(fi, buffer, 10);
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*
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* will read 10 a vertical line of 10 pixels starting at (x,y).
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*
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* Obviously, this sort of ugliness needs to be hidden away from
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* the casual user, with an appropriate set of higher level
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* functions.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/uio.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <i386/isa/isa_device.h>
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#include <i386/isa/ctxreg.h>
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#include <machine/ioctl_ctx.h>
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#include <machine/md_var.h>
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#ifndef COMPAT_OLDISA
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#error "The ctx device requires the old isa compatibility shims"
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#endif
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static int waitvb(int port);
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/* state flags */
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#define OPEN (0x01) /* device is open */
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static int ctxprobe(struct isa_device *devp);
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static int ctxattach(struct isa_device *devp);
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struct isa_driver ctxdriver = {
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INTR_TYPE_MISC,
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ctxprobe,
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ctxattach,
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"ctx"
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};
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COMPAT_ISA_DRIVER(ctx, ctxdriver);
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static d_open_t ctxopen;
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static d_close_t ctxclose;
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static d_read_t ctxread;
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static d_write_t ctxwrite;
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static d_ioctl_t ctxioctl;
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#define CDEV_MAJOR 40
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static struct cdevsw ctx_cdevsw = {
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.d_open = ctxopen,
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.d_close = ctxclose,
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.d_read = ctxread,
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.d_write = ctxwrite,
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.d_ioctl = ctxioctl,
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.d_name = "ctx",
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.d_maj = CDEV_MAJOR,
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};
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#define LUTSIZE 256 /* buffer size for Look Up Table (LUT) */
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#define PAGESIZE 65536 /* size of one video page, 1/4 of the screen */
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/*
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* Per unit shadow registers (because the dumb hardware is RO)
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*/
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struct ctx_soft_registers {
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u_char *lutp;
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u_char cp0;
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u_char cp1;
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u_char flag;
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int iobase;
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caddr_t maddr;
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int msize;
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};
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static int
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ctxprobe(struct isa_device * devp)
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{
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int status;
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if (inb(devp->id_iobase) == 0xff) /* 0xff only if board absent */
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status = 0;
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else {
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status = 1; /*XXX uses only one port? */
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}
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return (status);
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}
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static int
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ctxattach(struct isa_device * devp)
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{
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struct ctx_soft_registers *sr;
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dev_t dev;
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sr = malloc(sizeof *sr, M_DEVBUF, M_WAITOK | M_ZERO);
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sr->cp0 = 0; /* zero out the shadow registers */
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sr->cp1 = 0; /* and the open flag. wait for */
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sr->flag = 0; /* open to malloc the LUT space */
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sr->iobase = devp->id_iobase;
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sr->maddr = devp->id_maddr;
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sr->msize = devp->id_msize;
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dev = make_dev(&ctx_cdevsw, 0, 0, 0, 0600, "ctx%d", devp->id_unit);
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dev->si_drv1 = sr;
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return (1);
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}
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static int
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ctxopen(dev_t dev, int flags, int fmt, struct thread *td)
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{
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struct ctx_soft_registers *sr;
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int i;
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sr = dev->si_drv1;
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if (sr->flag != 0) /* someone has already opened us */
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return (EBUSY);
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/* get space for the LUT buffer */
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sr->lutp = malloc(LUTSIZE, M_DEVBUF, M_WAITOK);
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if (sr->lutp == NULL)
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return (ENOMEM);
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sr->flag = OPEN;
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/*
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Set up the shadow registers. We don't actually write these
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values to the control ports until after we finish loading the
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lookup table.
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*/
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sr->cp0 |= SEE_STORED_VIDEO;
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if ((kvtop(sr->maddr) == 0xB0000) || (kvtop(sr->maddr) == 0xE0000))
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sr->cp1 |= AB_SELECT; /* map to B or E if necessary */
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/* but don't enable RAM */
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/*
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Set up the lookup table initially so that it is transparent.
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*/
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outb(sr->iobase + ctx_cp0, (u_char) 0);
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outb(sr->iobase + ctx_cp1, (u_char) (LUT_LOAD_ENABLE | BLANK_DISPLAY));
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for (i = 0; i < LUTSIZE; i++) {
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outb(sr->iobase + ctx_lutaddr, (u_char) i);
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sr->lutp[i] = (u_char) i;
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outb(sr->iobase + ctx_lutdata, (u_char) sr->lutp[i]);
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}
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/*
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Disable LUT loading, and push the data in the shadow
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registers into the control ports.
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*/
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outb(sr->iobase + ctx_cp0, sr->cp0);
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outb(sr->iobase + ctx_cp1, sr->cp1);
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return (0); /* successful open. All ready to go. */
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}
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static int
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ctxclose(dev_t dev, int flags, int fmt, struct thread *td)
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{
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struct ctx_soft_registers *sr;
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sr = dev->si_drv1;
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sr->flag = 0;
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free(sr->lutp, M_DEVBUF);
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sr->lutp = NULL;
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return (0);
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}
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static int
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ctxwrite(dev_t dev, struct uio * uio, int ioflag)
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{
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int status = 0;
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int page, count, offset;
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struct ctx_soft_registers *sr;
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sr = dev->si_drv1;
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if (uio->uio_offset < 0)
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return (EINVAL);
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if (uio->uio_offset >= 4 * PAGESIZE)
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page = 4; /* EOF */
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else
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page = (u_int)uio->uio_offset / PAGESIZE;
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offset = (u_int)uio->uio_offset % PAGESIZE;
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count = min(uio->uio_resid, PAGESIZE - offset);
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while ((page >= 0) && (page <= 3) && (count > 0)) {
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sr->cp0 &= ~3;
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sr->cp0 |= page;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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/*
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Before doing the uiomove, we need to "connect" the frame buffer
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ram to the machine bus. This is done here so that we can have
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several different boards installed, all sharing the same memory
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space... each board is only "connected" to the bus when its memory
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is actually being read or written. All my instincts tell me that
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I should disable interrupts here, so I have done so.
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*/
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disable_intr();
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sr->cp1 |= RAM_ENABLE;
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outb(sr->iobase + ctx_cp1, sr->cp1);
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status = uiomove(sr->maddr + offset, count, uio);
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sr->cp1 &= ~RAM_ENABLE;
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outb(sr->iobase + ctx_cp1, sr->cp1);
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enable_intr();
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page = (u_int)uio->uio_offset / PAGESIZE;
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offset = (u_int)uio->uio_offset % PAGESIZE;
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count = min(uio->uio_resid, PAGESIZE - offset);
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}
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if (uio->uio_resid > 0)
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return (ENOSPC);
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else
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return (status);
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}
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static int
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ctxread(dev_t dev, struct uio * uio, int ioflag)
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{
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int status = 0;
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int page, count, offset;
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struct ctx_soft_registers *sr;
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sr = dev->si_drv1;
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if (uio->uio_offset < 0)
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return (EINVAL);
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if (uio->uio_offset >= 4 * PAGESIZE)
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page = 4; /* EOF */
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else
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page = (u_int)uio->uio_offset / PAGESIZE;
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offset = (u_int)uio->uio_offset % PAGESIZE;
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count = min(uio->uio_resid, PAGESIZE - offset);
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while ((page >= 0) && (page <= 3) && (count > 0)) {
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sr->cp0 &= ~3;
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sr->cp0 |= page;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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/*
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Before doing the uiomove, we need to "connect" the frame buffer
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ram to the machine bus. This is done here so that we can have
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several different boards installed, all sharing the same memory
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space... each board is only "connected" to the bus when its memory
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is actually being read or written. All my instincts tell me that
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I should disable interrupts here, so I have done so.
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*/
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disable_intr();
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sr->cp1 |= RAM_ENABLE;
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outb(sr->iobase + ctx_cp1, sr->cp1);
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status = uiomove(sr->maddr + offset, count, uio);
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sr->cp1 &= ~RAM_ENABLE;
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outb(sr->iobase + ctx_cp1, sr->cp1);
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enable_intr();
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page = (u_int)uio->uio_offset / PAGESIZE;
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offset = (u_int)uio->uio_offset % PAGESIZE;
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count = min(uio->uio_resid, PAGESIZE - offset);
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}
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if (uio->uio_resid > 0)
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return (ENOSPC);
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else
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return (status);
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}
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static int
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ctxioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct thread *td)
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{
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int error;
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int i;
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struct ctx_soft_registers *sr;
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error = 0;
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sr = dev->si_drv1;
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switch (cmd) {
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case CTX_LIVE:
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sr->cp0 &= ~SEE_STORED_VIDEO;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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break;
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case CTX_GRAB:
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sr->cp0 &= ~SEE_STORED_VIDEO;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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sr->cp0 |= ACQUIRE;
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if (waitvb(sr->iobase)) /* wait for vert blank to start
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* acquire */
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error = ENODEV;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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if (waitvb(sr->iobase)) /* wait for two more to finish acquire */
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error = ENODEV;
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if (waitvb(sr->iobase))
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error = ENODEV;
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sr->cp0 &= ~ACQUIRE; /* turn off acquire and turn on
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* display */
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sr->cp0 |= SEE_STORED_VIDEO;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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break;
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case CTX_H_ORGANIZE:
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sr->cp0 &= ~PAGE_ROTATE;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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break;
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case CTX_V_ORGANIZE:
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sr->cp0 |= PAGE_ROTATE;
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outb(sr->iobase + ctx_cp0, sr->cp0);
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break;
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case CTX_SET_LUT:
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bcopy((u_char *) data, sr->lutp, LUTSIZE);
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outb(sr->iobase + ctx_cp0, (u_char) 0);
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outb(sr->iobase + ctx_cp1, (u_char) (LUT_LOAD_ENABLE | BLANK_DISPLAY));
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for (i = 0; i < LUTSIZE; i++) {
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outb(sr->iobase + ctx_lutaddr, i);
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outb(sr->iobase + ctx_lutdata, sr->lutp[i]);
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}
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outb(sr->iobase + ctx_cp0, sr->cp0); /* restore control
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* registers */
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outb(sr->iobase + ctx_cp1, sr->cp1);
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break;
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case CTX_GET_LUT:
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bcopy(sr->lutp, (u_char *) data, LUTSIZE);
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break;
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default:
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error = ENODEV;
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}
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return (error);
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}
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static int
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waitvb(int port)
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{ /* wait for a vertical blank, */
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if (inb(port) == 0xff) /* 0xff means no board present */
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return (1);
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while ((inb(port) & VERTICAL_BLANK) != 0) {
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}
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while ((inb(port) & VERTICAL_BLANK) == 0) {
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}
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return (0);
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}
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