ca950537bb
On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
101 lines
3.4 KiB
C
101 lines
3.4 KiB
C
/*-
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _NLM_HAL_GBU_H__
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#define _NLM_HAL_GBU_H__
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/* Global Bus Unit (GBU) for flash Specific registers */
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#define GBU_CS_BASEADDR(cs) (0x0+cs)
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#define GBU_CS0_BASEADDR 0x0
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#define GBU_CS1_BASEADDR 0x1
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#define GBU_CS2_BASEADDR 0x2
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#define GBU_CS3_BASEADDR 0x3
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#define GBU_CS4_BASEADDR 0x4
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#define GBU_CS5_BASEADDR 0x5
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#define GBU_CS6_BASEADDR 0x6
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#define GBU_CS7_BASEADDR 0x7
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#define GBU_CS_BASELIMIT(cs) (0x8+cs)
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#define GBU_CS0_BASELIMIT 0x8
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#define GBU_CS1_BASELIMIT 0x9
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#define GBU_CS2_BASELIMIT 0xa
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#define GBU_CS3_BASELIMIT 0xb
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#define GBU_CS4_BASELIMIT 0xc
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#define GBU_CS5_BASELIMIT 0xd
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#define GBU_CS6_BASELIMIT 0xe
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#define GBU_CS7_BASELIMIT 0xf
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#define GBU_CS_DEVPARAM(cs) (0x10+cs)
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#define GBU_CS0_DEVPARAM 0x10
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#define GBU_CS1_DEVPARAM 0x11
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#define GBU_CS2_DEVPARAM 0x12
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#define GBU_CS3_DEVPARAM 0x13
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#define GBU_CS4_DEVPARAM 0x14
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#define GBU_CS5_DEVPARAM 0x15
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#define GBU_CS6_DEVPARAM 0x16
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#define GBU_CS7_DEVPARAM 0x17
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#define GBU_CS_DEVTIME0(cs) (0x18+cs)
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#define GBU_CS0_DEVTIME0 0x18
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#define GBU_CS1_DEVTIME0 0x1a
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#define GBU_CS2_DEVTIME0 0x1c
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#define GBU_CS3_DEVTIME0 0x1e
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#define GBU_CS4_DEVTIME0 0x20
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#define GBU_CS5_DEVTIME0 0x22
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#define GBU_CS6_DEVTIME0 0x24
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#define GBU_CS7_DEVTIME0 0x26
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#define GBU_CS_DEVTIME1(cs) (0x19+cs)
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#define GBU_CS0_DEVTIME1 0x19
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#define GBU_CS1_DEVTIME1 0x1b
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#define GBU_CS2_DEVTIME1 0x1d
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#define GBU_CS3_DEVTIME1 0x1f
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#define GBU_CS4_DEVTIME1 0x21
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#define GBU_CS5_DEVTIME1 0x23
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#define GBU_CS6_DEVTIME1 0x25
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#define GBU_CS7_DEVTIME1 0x27
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#define GBU_SYSCTRL 0x28
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#define GBU_BYTESWAP 0x29
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#define GBU_DI_TIMEOUT_VAL 0x2d
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#define GBU_INTSTAT 0x2e
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#define GBU_INTEN 0x2f
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#define GBU_STATUS 0x30
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#define GBU_ERRLOG0 0x2a
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#define GBU_ERRLOG1 0x2b
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#define GBU_ERRLOG2 0x2c
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_read_gbu_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_gbu_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_gbu_pcibase(node) \
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nlm_pcicfg_base(XLP_IO_NOR_OFFSET(node))
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#define nlm_get_gbu_regbase(node) \
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(nlm_get_gbu_pcibase(node) + XLP_IO_PCI_HDRSZ)
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#endif /* !LOCORE && !__ASSEMBLY__ */
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#endif /* _NLM_HAL_GBU_H__ */
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