Marcin Wojtas b8cb0864dc Add QorIQ platform clockgen driver. ... This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs. As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts. This is a preparation patch for NXP LS1046A SoC support. Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351		2020-05-25 14:31:32 +00:00
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acpica	Ignore the SMMUv3 and PMCG interrupt controller in the IORT tables	2020-01-31 09:51:38 +00:00
arm64	Stop performing a full icache sync when the DIC and IDC flags are set	2020-05-19 16:04:27 +00:00
broadcom	Add genet driver for Raspberry Pi 4B Ethernet	2020-04-22 00:42:10 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
cloudabi64	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
conf	Add genet driver for Raspberry Pi 4B Ethernet	2020-04-22 00:42:10 +00:00
coresight	Extract eventfilter declarations to sys/_eventfilter.h	2019-05-20 00:38:23 +00:00
include	Stop performing a full icache sync when the DIC and IDC flags are set	2020-05-19 16:04:27 +00:00
intel	Add support for Intel Stratix 10 platform.	2019-09-13 16:50:57 +00:00
linux	Convert canary, execpathp, and pagesizes to pointers.	2020-04-16 21:53:17 +00:00
qoriq/clk	Add QorIQ platform clockgen driver.	2020-05-25 14:31:32 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	Don't try to re-initialize already preseted regulator.	2020-04-29 13:45:21 +00:00