ad020198ff
The DIC and IDC bits in the CTR_EL0 register signal to the kernel when it can relax the instruction cache synchronisation operations. The IDC bit means we can relax cleaning the data cache to the point of unification while the DIC bit means we don't need to invalidate the instruction cache for data coherence. In both cases an appropriate barrier is still needed. For now only implement the case where both bits are set, as is the case on the Neoverse-N1 as used in the Amazon AWS Graviton 2 CPU. Note that this behaviour is a optional on the N1 so we may later need to implement only one or the other bit being set. There is a tunable to disable each flag on boot. Testing on a 4 core Graviton 2 instance found a significant improvement in sys and real time when running "make buildkernel -j4", with no significant difference in user time. Reviewed by: markj Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D24853 |
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