5b628c272e
controllers. ICH based controllers are treated as 82559. 82557, earlier revision of 82558 and 82559ER have no WOL capability. o WOL support requires help of a firmware so add check whether hardware is capable of handling magic frames by reading EEPROM. o Enable accepting WOL frames only when hardware is about to suspend or shutdown. Previously fxp(4) used to allow receipt of magic frame under normal operation mode which could cause hardware hang if magic frame is received by hardware. Datasheet clearly states driver should not allow WOL frames under normal operation mode. o Disable WOL frame reception in device attach so have fxp(4) immunize against system hang which can be triggered by magic packets when the hardware is not in fully initialized state. o Don't reset all hardware configuration data in fxp_stop() otherwise important configuration data is lost and this would reset WOL configuration to default state which in turn cause hardware hang on receipt of magic frames. To fix the issue, preserve hardware configuration data by issuing a selective reset. o Explicitly disable interrupts after issuing selective reset as reset may unmask interrupts. Tested by: Alexey Shuvaev < shuvaev <> physik DOT uni-wuerzburg DOT de >
475 lines
14 KiB
C
475 lines
14 KiB
C
/*-
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* Copyright (c) 1995, David Greenman
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* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define FXP_VENDORID_INTEL 0x8086
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#define FXP_PCI_MMBA 0x10
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#define FXP_PCI_IOBA 0x14
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/*
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* Control/status registers.
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*/
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#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
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#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
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#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
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#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
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#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
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#define FXP_CSR_PORT 8 /* port (4 bytes) */
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#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
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#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
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#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
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#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */
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#define FXP_CSR_PMDR 0x1B /* power management driver (1 byte) */
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#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */
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/*
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* FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
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*
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* volatile uint8_t :2,
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* scb_rus:4,
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* scb_cus:2;
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*/
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#define FXP_PORT_SOFTWARE_RESET 0
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#define FXP_PORT_SELFTEST 1
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#define FXP_PORT_SELECTIVE_RESET 2
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#define FXP_PORT_DUMP 3
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#define FXP_SCB_RUS_IDLE 0
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#define FXP_SCB_RUS_SUSPENDED 1
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#define FXP_SCB_RUS_NORESOURCES 2
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#define FXP_SCB_RUS_READY 4
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#define FXP_SCB_RUS_SUSP_NORBDS 9
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#define FXP_SCB_RUS_NORES_NORBDS 10
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#define FXP_SCB_RUS_READY_NORBDS 12
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#define FXP_SCB_CUS_IDLE 0
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#define FXP_SCB_CUS_SUSPENDED 1
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#define FXP_SCB_CUS_ACTIVE 2
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#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */
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#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */
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#define FXP_SCB_INTMASK_FCP 0x04
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#define FXP_SCB_INTMASK_ER 0x08
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#define FXP_SCB_INTMASK_RNR 0x10
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#define FXP_SCB_INTMASK_CNA 0x20
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#define FXP_SCB_INTMASK_FR 0x40
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#define FXP_SCB_INTMASK_CXTNO 0x80
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#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */
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#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */
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#define FXP_SCB_STATACK_SWI 0x04
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#define FXP_SCB_STATACK_MDI 0x08
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#define FXP_SCB_STATACK_RNR 0x10
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#define FXP_SCB_STATACK_CNA 0x20
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#define FXP_SCB_STATACK_FR 0x40
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#define FXP_SCB_STATACK_CXTNO 0x80
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#define FXP_SCB_COMMAND_CU_NOP 0x00
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#define FXP_SCB_COMMAND_CU_START 0x10
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#define FXP_SCB_COMMAND_CU_RESUME 0x20
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#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
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#define FXP_SCB_COMMAND_CU_DUMP 0x50
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#define FXP_SCB_COMMAND_CU_BASE 0x60
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#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
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#define FXP_SCB_COMMAND_RU_NOP 0
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#define FXP_SCB_COMMAND_RU_START 1
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#define FXP_SCB_COMMAND_RU_RESUME 2
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#define FXP_SCB_COMMAND_RU_ABORT 4
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#define FXP_SCB_COMMAND_RU_LOADHDS 5
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#define FXP_SCB_COMMAND_RU_BASE 6
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#define FXP_SCB_COMMAND_RU_RBDRESUME 7
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/*
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* Command block definitions
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*/
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struct fxp_cb_nop {
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uint16_t cb_status;
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uint16_t cb_command;
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uint32_t link_addr;
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};
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struct fxp_cb_ias {
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uint16_t cb_status;
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uint16_t cb_command;
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uint32_t link_addr;
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uint8_t macaddr[6];
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};
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/* I hate bit-fields :-( */
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#if BYTE_ORDER == LITTLE_ENDIAN
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#define __FXP_BITFIELD2(a, b) a, b
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#define __FXP_BITFIELD3(a, b, c) a, b, c
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#define __FXP_BITFIELD4(a, b, c, d) a, b, c, d
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#define __FXP_BITFIELD5(a, b, c, d, e) a, b, c, d, e
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#define __FXP_BITFIELD6(a, b, c, d, e, f) a, b, c, d, e, f
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#define __FXP_BITFIELD7(a, b, c, d, e, f, g) a, b, c, d, e, f, g
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#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) a, b, c, d, e, f, g, h
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#else
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#define __FXP_BITFIELD2(a, b) b, a
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#define __FXP_BITFIELD3(a, b, c) c, b, a
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#define __FXP_BITFIELD4(a, b, c, d) d, c, b, a
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#define __FXP_BITFIELD5(a, b, c, d, e) e, d, c, b, a
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#define __FXP_BITFIELD6(a, b, c, d, e, f) f, e, d, c, b, a
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#define __FXP_BITFIELD7(a, b, c, d, e, f, g) g, f, e, d, c, b, a
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#define __FXP_BITFIELD8(a, b, c, d, e, f, g, h) h, g, f, e, d, c, b, a
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#endif
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struct fxp_cb_config {
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uint16_t cb_status;
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uint16_t cb_command;
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uint32_t link_addr;
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/* Bytes 0 - 21 -- common to all i8255x */
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u_int __FXP_BITFIELD2(byte_count:6, :2);
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u_int __FXP_BITFIELD3(rx_fifo_limit:4, tx_fifo_limit:3, :1);
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uint8_t adaptive_ifs;
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u_int __FXP_BITFIELD5(mwi_enable:1, /* 8,9 */
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type_enable:1, /* 8,9 */
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read_align_en:1, /* 8,9 */
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end_wr_on_cl:1, /* 8,9 */
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:4);
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u_int __FXP_BITFIELD2(rx_dma_bytecount:7, :1);
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u_int __FXP_BITFIELD2(tx_dma_bytecount:7, dma_mbce:1);
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u_int __FXP_BITFIELD8(late_scb:1, /* 7 */
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direct_dma_dis:1, /* 8,9 */
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tno_int_or_tco_en:1, /* 7,9 */
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ci_int:1,
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ext_txcb_dis:1, /* 8,9 */
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ext_stats_dis:1, /* 8,9 */
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keep_overrun_rx:1,
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save_bf:1);
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u_int __FXP_BITFIELD6(disc_short_rx:1,
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underrun_retry:2,
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:2,
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ext_rfa:1, /* 550 */
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two_frames:1, /* 8,9 */
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dyn_tbd:1); /* 8,9 */
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u_int __FXP_BITFIELD3(mediatype:1, /* 7 */
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:6,
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csma_dis:1); /* 8,9 */
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u_int __FXP_BITFIELD6(tcp_udp_cksum:1, /* 9 */
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:3,
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vlan_tco:1, /* 8,9 */
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link_wake_en:1, /* 8,9 */
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arp_wake_en:1, /* 8 */
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mc_wake_en:1); /* 8 */
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u_int __FXP_BITFIELD4(:3,
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nsai:1,
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preamble_length:2,
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loopback:2);
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u_int __FXP_BITFIELD2(linear_priority:3, /* 7 */
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:5);
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u_int __FXP_BITFIELD3(linear_pri_mode:1, /* 7 */
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:3,
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interfrm_spacing:4);
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u_int :8;
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u_int :8;
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u_int __FXP_BITFIELD8(promiscuous:1,
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bcast_disable:1,
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wait_after_win:1, /* 8,9 */
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:1,
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ignore_ul:1, /* 8,9 */
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crc16_en:1, /* 9 */
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:1,
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crscdt:1);
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u_int fc_delay_lsb:8; /* 8,9 */
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u_int fc_delay_msb:8; /* 8,9 */
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u_int __FXP_BITFIELD6(stripping:1,
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padding:1,
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rcv_crc_xfer:1,
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long_rx_en:1, /* 8,9 */
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pri_fc_thresh:3, /* 8,9 */
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:1);
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u_int __FXP_BITFIELD8(ia_wake_en:1, /* 8 */
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magic_pkt_dis:1, /* 8,9,!9ER */
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tx_fc_dis:1, /* 8,9 */
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rx_fc_restop:1, /* 8,9 */
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rx_fc_restart:1, /* 8,9 */
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fc_filter:1, /* 8,9 */
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force_fdx:1,
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fdx_pin_en:1);
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u_int __FXP_BITFIELD4(:5,
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pri_fc_loc:1, /* 8,9 */
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multi_ia:1,
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:1);
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u_int __FXP_BITFIELD3(:3, mc_all:1, :4);
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/* Bytes 22 - 31 -- i82550 only */
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u_int __FXP_BITFIELD3(gamla_rx:1,
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vlan_drop_en:1,
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:6);
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uint8_t pad[9];
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};
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#define MAXMCADDR 80
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struct fxp_cb_mcs {
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uint16_t cb_status;
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uint16_t cb_command;
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uint32_t link_addr;
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uint16_t mc_cnt;
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uint8_t mc_addr[MAXMCADDR][6];
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};
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#define MAXUCODESIZE 192
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struct fxp_cb_ucode {
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uint16_t cb_status;
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uint16_t cb_command;
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uint32_t link_addr;
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uint32_t ucode[MAXUCODESIZE];
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};
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/*
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* Number of DMA segments in a TxCB.
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*/
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#define FXP_NTXSEG 32
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struct fxp_tbd {
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uint32_t tb_addr;
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uint32_t tb_size;
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};
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struct fxp_ipcb {
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/*
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* The following fields are valid only when
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* using the IPCB command block for TX checksum offload
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* (and TCP large send, VLANs, and (I think) IPsec). To use
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* them, you must enable extended TxCBs (available only
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* on the 82559 and later) and use the IPCBXMIT command.
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* Note that Intel defines the IPCB to be 32 bytes long,
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* the last 8 bytes of which comprise the first entry
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* in the TBD array (see note below). This means we only
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* have to define 8 extra bytes here.
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*/
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uint16_t ipcb_schedule_low;
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uint8_t ipcb_ip_schedule;
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uint8_t ipcb_ip_activation_high;
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uint16_t ipcb_vlan_id;
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uint8_t ipcb_ip_header_offset;
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uint8_t ipcb_tcp_header_offset;
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};
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struct fxp_cb_tx {
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uint16_t cb_status;
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uint16_t cb_command;
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uint32_t link_addr;
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uint32_t tbd_array_addr;
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uint16_t byte_count;
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uint8_t tx_threshold;
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uint8_t tbd_number;
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/*
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* The following structure isn't actually part of the TxCB,
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* unless the extended TxCB feature is being used. In this
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* case, the first two elements of the structure below are
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* fetched along with the TxCB.
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*/
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union {
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struct fxp_ipcb ipcb;
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struct fxp_tbd tbd[FXP_NTXSEG + 1];
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} tx_cb_u;
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};
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#define tbd tx_cb_u.tbd
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#define ipcb_schedule_low tx_cb_u.ipcb.ipcb_schedule_low
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#define ipcb_ip_schedule tx_cb_u.ipcb.ipcb_ip_schedule
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#define ipcb_ip_activation_high tx_cb_u.ipcb.ipcb_ip_activation_high
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#define ipcb_vlan_id tx_cb_u.ipcb.ipcb_vlan_id
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#define ipcb_ip_header_offset tx_cb_u.ipcb.ipcb_ip_header_offset
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#define ipcb_tcp_header_offset tx_cb_u.ipcb.ipcb_tcp_header_offset
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/*
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* IPCB field definitions
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*/
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#define FXP_IPCB_IP_CHECKSUM_ENABLE 0x10
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#define FXP_IPCB_TCPUDP_CHECKSUM_ENABLE 0x20
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#define FXP_IPCB_TCP_PACKET 0x40
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#define FXP_IPCB_LARGESEND_ENABLE 0x80
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#define FXP_IPCB_HARDWAREPARSING_ENABLE 0x01
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#define FXP_IPCB_INSERTVLAN_ENABLE 0x02
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/*
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* Control Block (CB) definitions
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*/
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/* status */
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#define FXP_CB_STATUS_OK 0x2000
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#define FXP_CB_STATUS_C 0x8000
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/* commands */
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#define FXP_CB_COMMAND_NOP 0x0
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#define FXP_CB_COMMAND_IAS 0x1
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#define FXP_CB_COMMAND_CONFIG 0x2
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#define FXP_CB_COMMAND_MCAS 0x3
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#define FXP_CB_COMMAND_XMIT 0x4
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#define FXP_CB_COMMAND_UCODE 0x5
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#define FXP_CB_COMMAND_DUMP 0x6
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#define FXP_CB_COMMAND_DIAG 0x7
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#define FXP_CB_COMMAND_LOADFILT 0x8
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#define FXP_CB_COMMAND_IPCBXMIT 0x9
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/* command flags */
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#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
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#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
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#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
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#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
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/*
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* RFA definitions
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*/
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struct fxp_rfa {
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uint16_t rfa_status;
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uint16_t rfa_control;
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uint32_t link_addr;
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uint32_t rbd_addr;
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uint16_t actual_size;
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uint16_t size;
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/*
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* The following fields are only available when using
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* extended receive mode on an 82550/82551 chipset.
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*/
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uint16_t rfax_vlan_id;
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uint8_t rfax_rx_parser_sts;
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uint8_t rfax_rsvd0;
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uint16_t rfax_security_sts;
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uint8_t rfax_csum_sts;
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uint8_t rfax_zerocopy_sts;
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uint8_t rfax_pad[8];
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} __packed;
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#define FXP_RFAX_LEN 16
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#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
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#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
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#define FXP_RFA_STATUS_NOAMATCH 0x0004 /* 1 = doesn't match anything */
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#define FXP_RFA_STATUS_PARSE 0x0008 /* pkt parse ok (82550/1 only) */
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#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
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#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
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#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
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#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
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#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
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#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
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#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
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#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
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#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
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#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
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#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
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#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
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#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
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/* Bits in the 'csum_sts' byte */
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#define FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID 0x10
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#define FXP_RFDX_CS_TCPUDP_CSUM_VALID 0x20
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#define FXP_RFDX_CS_IP_CSUM_BIT_VALID 0x01
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#define FXP_RFDX_CS_IP_CSUM_VALID 0x02
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/* Bits in the 'packet parser' byte */
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#define FXP_RFDX_P_PARSE_BIT 0x08
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#define FXP_RFDX_P_CSUM_PROTOCOL_MASK 0x03
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#define FXP_RFDX_P_TCP_PACKET 0x00
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#define FXP_RFDX_P_UDP_PACKET 0x01
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#define FXP_RFDX_P_IP_PACKET 0x03
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/*
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* Statistics dump area definitions
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*/
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struct fxp_stats {
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uint32_t tx_good;
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uint32_t tx_maxcols;
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uint32_t tx_latecols;
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uint32_t tx_underruns;
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uint32_t tx_lostcrs;
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uint32_t tx_deffered;
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uint32_t tx_single_collisions;
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uint32_t tx_multiple_collisions;
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uint32_t tx_total_collisions;
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uint32_t rx_good;
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uint32_t rx_crc_errors;
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uint32_t rx_alignment_errors;
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uint32_t rx_rnr_errors;
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uint32_t rx_overrun_errors;
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uint32_t rx_cdt_errors;
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uint32_t rx_shortframes;
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uint32_t completion_status;
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};
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#define FXP_STATS_DUMP_COMPLETE 0xa005
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#define FXP_STATS_DR_COMPLETE 0xa007
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/*
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* Serial EEPROM control register bits
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*/
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#define FXP_EEPROM_EESK 0x01 /* shift clock */
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#define FXP_EEPROM_EECS 0x02 /* chip select */
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#define FXP_EEPROM_EEDI 0x04 /* data in */
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#define FXP_EEPROM_EEDO 0x08 /* data out */
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/*
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* Serial EEPROM opcodes, including start bit
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*/
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#define FXP_EEPROM_OPC_ERASE 0x4
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#define FXP_EEPROM_OPC_WRITE 0x5
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#define FXP_EEPROM_OPC_READ 0x6
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/*
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* Management Data Interface opcodes
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*/
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#define FXP_MDI_WRITE 0x1
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#define FXP_MDI_READ 0x2
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/*
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* PHY device types
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*/
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#define FXP_PHY_DEVICE_MASK 0x3f00
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#define FXP_PHY_SERIAL_ONLY 0x8000
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#define FXP_PHY_NONE 0
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#define FXP_PHY_82553A 1
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#define FXP_PHY_82553C 2
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#define FXP_PHY_82503 3
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#define FXP_PHY_DP83840 4
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#define FXP_PHY_80C240 5
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#define FXP_PHY_80C24 6
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#define FXP_PHY_82555 7
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#define FXP_PHY_DP83840A 10
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#define FXP_PHY_82555B 11
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/*
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* Chip revision values.
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*/
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#define FXP_REV_82557 1 /* catchall 82557 chip type */
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#define FXP_REV_82558_A4 4 /* 82558 A4 stepping */
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#define FXP_REV_82558_B0 5 /* 82558 B0 stepping */
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#define FXP_REV_82559_A0 8 /* 82559 A0 stepping */
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#define FXP_REV_82559S_A 9 /* 82559S A stepping */
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#define FXP_REV_82550 12
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#define FXP_REV_82550_C 13 /* 82550 C stepping */
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#define FXP_REV_82551_E 14 /* 82551 */
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#define FXP_REV_82551_F 15 /* 82551 */
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#define FXP_REV_82551_10 16 /* 82551 */
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