e8c81f0320
If package-level control is present, we default to using it. Per-core software control may be enabled by setting the machdep.hwpstate_pkg_ctrl tunable to "0" in loader.conf(5).
98 lines
3.3 KiB
Groff
98 lines
3.3 KiB
Groff
.\"
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.\" Copyright (c) 2019 Intel Corporation
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 1, 2020
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.Dt HWPSTATE_INTEL 4
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.Os
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.Sh NAME
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.Nm hwpstate_intel
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.Nd Intel Speed Shift Technology driver
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.Sh SYNOPSIS
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To compile this driver into your kernel
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place the following line in your kernel
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configuration file:
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.Bd -ragged -offset indent
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.Cd "device cpufreq"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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driver provides support for hardware-controlled performance states on Intel
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platforms, also known as Intel Speed Shift Technology.
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.Sh LOADER TUNABLES
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.Bl -tag -width indent
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.It Va hint.hwpstate_intel.0.disabled
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Can be used to disable
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.Nm ,
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allowing other compatible drivers to manage performance states, like
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.Xr est 4 .
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Defaults to
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.Dv Qq 0
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(enabled).
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.It Va machdep.hwpstate_pkg_ctrl
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Selects between package-level control (the default) and per-core control.
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.Dv Qq 1
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selects package-level control and
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.Dv Qq 0
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selects core-level control.
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.El
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.Sh SYSCTL VARIABLES
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The following
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.Xr sysctl 8
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values are available
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.Bl -tag -width indent
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.It Va dev.hwpstate_intel.%d.\%desc
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Describes the attached driver
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.It dev.hwpstate_intel.0.%desc: Intel Speed Shift
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.It Va dev.hwpstate_intel.%d.\%driver
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Driver in use, always hwpstate_intel.
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.It dev.hwpstate_intel.0.%driver: hwpstate_intel
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.It Va dev.hwpstate_intel.%d.\%parent
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.It dev.hwpstate_intel.0.%parent: cpu0
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The cpu that is exposing these frequencies.
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For example
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.Va cpu0 .
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.It Va dev.hwpstate_intel.%d.epp
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Energy/Performance Preference.
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Valid values range from 0 to 100.
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Setting this field conveys a hint to the hardware regarding a preference towards
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performance (at value 0), energy efficiency (at value 100), or somewhere in
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between.
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.It dev.hwpstate_intel.0.epp: 0
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.El
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.Sh COMPATIBILITY
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.Nm
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is only found on supported Intel CPUs.
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.Sh SEE ALSO
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.Xr cpufreq 4
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.Rs
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.%T "Intel 64 and IA-32 Architectures Software Developer Manuals"
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.%U "http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html"
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.Re
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.Sh AUTHORS
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This manual page was written by
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.An D Scott Phillips Aq Mt scottph@FreeBSD.org .
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