b9eabb421b
in that it provides an abstract (intermediate) representation for instructions. This significantly improves working with instructions such as emulation of instructions that are not implemented by the hardware (e.g. long branch) or enhancing implemented instructions (e.g. handling of misaligned memory accesses). Not to mention that it's much easier to print instructions. Functions are included that provide a textual representation for opcodes, completers and operands. The disassembler supports all ia64 instructions defined by revision 2.1 of the SDM (Oct 2002).
326 lines
11 KiB
C
326 lines
11 KiB
C
/*
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* Copyright (c) 2000-2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DISASM_H_
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#define _DISASM_H_
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#ifndef _DISASM_INT_H_
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#define ASM_ADDITIONAL_OPCODES ASM_OP_NUMBER_OF_OPCODES
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#endif
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/* Application registers. */
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#define AR_K0 0
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#define AR_K1 1
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#define AR_K2 2
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#define AR_K3 3
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#define AR_K4 4
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#define AR_K5 5
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#define AR_K6 6
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#define AR_K7 7
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#define AR_RSC 16
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#define AR_BSP 17
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#define AR_BSPSTORE 18
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#define AR_RNAT 19
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#define AR_FCR 21
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#define AR_EFLAG 24
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#define AR_CSD 25
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#define AR_SSD 26
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#define AR_CFLG 27
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#define AR_FSR 28
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#define AR_FIR 29
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#define AR_FDR 30
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#define AR_CCV 32
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#define AR_UNAT 36
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#define AR_FPSR 40
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#define AR_ITC 44
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#define AR_PFS 64
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#define AR_LC 65
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#define AR_EC 66
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/* Control registers. */
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#define CR_DCR 0
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#define CR_ITM 1
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#define CR_IVA 2
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#define CR_PTA 8
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#define CR_IPSR 16
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#define CR_ISR 17
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#define CR_IIP 19
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#define CR_IFA 20
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#define CR_ITIR 21
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#define CR_IIPA 22
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#define CR_IFS 23
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#define CR_IIM 24
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#define CR_IHA 25
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#define CR_LID 64
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#define CR_IVR 65
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#define CR_TPR 66
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#define CR_EOI 67
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#define CR_IRR0 68
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#define CR_IRR1 69
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#define CR_IRR2 70
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#define CR_IRR3 71
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#define CR_ITV 72
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#define CR_PMV 73
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#define CR_CMCV 74
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#define CR_LRR0 80
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#define CR_LRR1 81
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enum asm_cmpltr_class {
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ASM_CC_NONE,
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ASM_CC_ACLR,
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ASM_CC_BSW, ASM_CC_BTYPE, ASM_CC_BWH,
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ASM_CC_CHK, ASM_CC_CLRRRB, ASM_CC_CREL, ASM_CC_CTYPE,
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ASM_CC_DEP, ASM_CC_DH,
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ASM_CC_FC, ASM_CC_FCREL, ASM_CC_FCTYPE, ASM_CC_FCVT, ASM_CC_FLDTYPE,
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ASM_CC_FMERGE, ASM_CC_FREL, ASM_CC_FSWAP,
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ASM_CC_GETF,
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ASM_CC_IH, ASM_CC_INVALA, ASM_CC_IPWH, ASM_CC_ITC, ASM_CC_ITR,
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ASM_CC_LDHINT, ASM_CC_LDTYPE, ASM_CC_LFETCH, ASM_CC_LFHINT,
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ASM_CC_LFTYPE, ASM_CC_LR,
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ASM_CC_MF, ASM_CC_MOV, ASM_CC_MWH,
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ASM_CC_PAVG, ASM_CC_PC, ASM_CC_PH, ASM_CC_PREL, ASM_CC_PRTYPE,
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ASM_CC_PTC, ASM_CC_PTR, ASM_CC_PVEC,
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ASM_CC_SAT, ASM_CC_SEM, ASM_CC_SETF, ASM_CC_SF, ASM_CC_SRLZ,
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ASM_CC_STHINT, ASM_CC_STTYPE, ASM_CC_SYNC,
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ASM_CC_RW,
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ASM_CC_TREL, ASM_CC_TRUNC,
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ASM_CC_UNIT, ASM_CC_UNPACK, ASM_CC_UNS,
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ASM_CC_XMA
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};
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enum asm_cmpltr_type {
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ASM_CT_NONE,
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ASM_CT_COND = ASM_CT_NONE,
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ASM_CT_0, ASM_CT_1,
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ASM_CT_A, ASM_CT_ACQ, ASM_CT_AND,
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ASM_CT_B, ASM_CT_BIAS,
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ASM_CT_C_CLR, ASM_CT_C_CLR_ACQ, ASM_CT_C_NC, ASM_CT_CALL,
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ASM_CT_CEXIT, ASM_CT_CLOOP, ASM_CT_CLR, ASM_CT_CTOP,
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ASM_CT_D, ASM_CT_DC_DC, ASM_CT_DC_NT, ASM_CT_DPNT, ASM_CT_DPTK,
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ASM_CT_E, ASM_CT_EQ, ASM_CT_EXCL, ASM_CT_EXIT, ASM_CT_EXP,
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ASM_CT_F, ASM_CT_FAULT, ASM_CT_FEW, ASM_CT_FILL, ASM_CT_FX, ASM_CT_FXU,
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ASM_CT_G, ASM_CT_GA, ASM_CT_GE, ASM_CT_GT,
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ASM_CT_H, ASM_CT_HU,
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ASM_CT_I, ASM_CT_IA, ASM_CT_IMP,
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ASM_CT_L, ASM_CT_LE, ASM_CT_LOOP, ASM_CT_LR, ASM_CT_LT, ASM_CT_LTU,
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ASM_CT_M, ASM_CT_MANY,
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ASM_CT_NC, ASM_CT_NE, ASM_CT_NEQ, ASM_CT_NL, ASM_CT_NLE, ASM_CT_NLT,
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ASM_CT_NM, ASM_CT_NR, ASM_CT_NS, ASM_CT_NT_DC, ASM_CT_NT_NT,
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ASM_CT_NT_TK, ASM_CT_NT1, ASM_CT_NT2, ASM_CT_NTA, ASM_CT_NZ,
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ASM_CT_OR, ASM_CT_OR_ANDCM, ASM_CT_ORD,
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ASM_CT_PR,
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ASM_CT_R, ASM_CT_RAZ, ASM_CT_REL, ASM_CT_RET, ASM_CT_RW,
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ASM_CT_S, ASM_CT_S0, ASM_CT_S1, ASM_CT_S2, ASM_CT_S3, ASM_CT_SA,
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ASM_CT_SE, ASM_CT_SIG, ASM_CT_SPILL, ASM_CT_SPNT, ASM_CT_SPTK,
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ASM_CT_SSS,
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ASM_CT_TK_DC, ASM_CT_TK_NT, ASM_CT_TK_TK, ASM_CT_TRUNC,
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ASM_CT_U, ASM_CT_UNC, ASM_CT_UNORD, ASM_CT_USS, ASM_CT_UUS, ASM_CT_UUU,
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ASM_CT_W, ASM_CT_WEXIT, ASM_CT_WTOP,
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ASM_CT_X, ASM_CT_XF,
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ASM_CT_Z,
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};
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/* Completer. */
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struct asm_cmpltr {
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enum asm_cmpltr_class c_class;
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enum asm_cmpltr_type c_type;
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};
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/* Operand types. */
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enum asm_oper_type {
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ASM_OPER_NONE,
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ASM_OPER_AREG, /* = ar# */
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ASM_OPER_BREG, /* = b# */
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ASM_OPER_CPUID, /* = cpuid[r#] */
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ASM_OPER_CREG, /* = cr# */
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ASM_OPER_DBR, /* = dbr[r#] */
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ASM_OPER_DISP, /* IP relative displacement. */
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ASM_OPER_DTR, /* = dtr[r#] */
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ASM_OPER_FREG, /* = f# */
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ASM_OPER_GREG, /* = r# */
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ASM_OPER_IBR, /* = ibr[r#] */
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ASM_OPER_IMM, /* Immediate */
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ASM_OPER_IP, /* = ip */
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ASM_OPER_ITR, /* = itr[r#] */
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ASM_OPER_MEM, /* = [r#] */
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ASM_OPER_MSR, /* = msr[r#] */
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ASM_OPER_PKR, /* = pkr[r#] */
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ASM_OPER_PMC, /* = pmc[r#] */
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ASM_OPER_PMD, /* = pmd[r#] */
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ASM_OPER_PR, /* = pr */
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ASM_OPER_PR_ROT, /* = pr.rot */
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ASM_OPER_PREG, /* = p# */
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ASM_OPER_PSR, /* = psr */
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ASM_OPER_PSR_L, /* = psr.l */
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ASM_OPER_PSR_UM, /* = psr.um */
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ASM_OPER_RR /* = rr[r#] */
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};
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/* Operand */
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struct asm_oper {
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enum asm_oper_type o_type;
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int o_read:1;
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int o_write:1;
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uint64_t o_value;
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};
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/* Instruction formats. */
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enum asm_fmt {
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ASM_FMT_NONE,
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ASM_FMT_A = 0x0100,
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ASM_FMT_A1, ASM_FMT_A2, ASM_FMT_A3, ASM_FMT_A4,
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ASM_FMT_A5, ASM_FMT_A6, ASM_FMT_A7, ASM_FMT_A8,
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ASM_FMT_A9, ASM_FMT_A10,
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ASM_FMT_B = 0x0200,
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ASM_FMT_B1, ASM_FMT_B2, ASM_FMT_B3, ASM_FMT_B4,
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ASM_FMT_B5, ASM_FMT_B6, ASM_FMT_B7, ASM_FMT_B8,
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ASM_FMT_B9,
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ASM_FMT_F = 0x0300,
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ASM_FMT_F1, ASM_FMT_F2, ASM_FMT_F3, ASM_FMT_F4,
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ASM_FMT_F5, ASM_FMT_F6, ASM_FMT_F7, ASM_FMT_F8,
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ASM_FMT_F9, ASM_FMT_F10, ASM_FMT_F11, ASM_FMT_F12,
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ASM_FMT_F13, ASM_FMT_F14, ASM_FMT_F15,
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ASM_FMT_I = 0x0400,
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ASM_FMT_I1, ASM_FMT_I2, ASM_FMT_I3, ASM_FMT_I4,
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ASM_FMT_I5, ASM_FMT_I6, ASM_FMT_I7, ASM_FMT_I8,
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ASM_FMT_I9, ASM_FMT_I10, ASM_FMT_I11, ASM_FMT_I12,
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ASM_FMT_I13, ASM_FMT_I14, ASM_FMT_I15, ASM_FMT_I16,
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ASM_FMT_I17, ASM_FMT_I19, ASM_FMT_I20, ASM_FMT_I21,
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ASM_FMT_I22, ASM_FMT_I23, ASM_FMT_I24, ASM_FMT_I25,
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ASM_FMT_I26, ASM_FMT_I27, ASM_FMT_I28, ASM_FMT_I29,
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ASM_FMT_M = 0x0500,
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ASM_FMT_M1, ASM_FMT_M2, ASM_FMT_M3, ASM_FMT_M4,
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ASM_FMT_M5, ASM_FMT_M6, ASM_FMT_M7, ASM_FMT_M8,
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ASM_FMT_M9, ASM_FMT_M10, ASM_FMT_M11, ASM_FMT_M12,
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ASM_FMT_M13, ASM_FMT_M14, ASM_FMT_M15, ASM_FMT_M16,
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ASM_FMT_M17, ASM_FMT_M18, ASM_FMT_M19, ASM_FMT_M20,
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ASM_FMT_M21, ASM_FMT_M22, ASM_FMT_M23, ASM_FMT_M24,
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ASM_FMT_M25, ASM_FMT_M26, ASM_FMT_M27, ASM_FMT_M28,
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ASM_FMT_M29, ASM_FMT_M30, ASM_FMT_M31, ASM_FMT_M32,
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ASM_FMT_M33, ASM_FMT_M34, ASM_FMT_M35, ASM_FMT_M36,
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ASM_FMT_M37, ASM_FMT_M38, ASM_FMT_M39, ASM_FMT_M40,
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ASM_FMT_M41, ASM_FMT_M42, ASM_FMT_M43, ASM_FMT_M44,
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ASM_FMT_M45, ASM_FMT_M46,
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ASM_FMT_X = 0x0600,
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ASM_FMT_X1, ASM_FMT_X2, ASM_FMT_X3, ASM_FMT_X4
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};
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/* Instruction opcodes. */
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enum asm_op {
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ASM_OP_NONE,
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ASM_OP_ADD, ASM_OP_ADDL, ASM_OP_ADDP4, ASM_OP_ADDS, ASM_OP_ALLOC,
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ASM_OP_AND, ASM_OP_ANDCM,
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ASM_OP_BR, ASM_OP_BREAK, ASM_OP_BRL, ASM_OP_BRP, ASM_OP_BSW,
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ASM_OP_CHK, ASM_OP_CLRRRB, ASM_OP_CMP, ASM_OP_CMP4, ASM_OP_CMP8XCHG16,
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ASM_OP_CMPXCHG1, ASM_OP_CMPXCHG2, ASM_OP_CMPXCHG4, ASM_OP_CMPXCHG8,
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ASM_OP_COVER, ASM_OP_CZX1, ASM_OP_CZX2,
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ASM_OP_DEP,
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ASM_OP_EPC, ASM_OP_EXTR,
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ASM_OP_FAMAX, ASM_OP_FAMIN, ASM_OP_FAND, ASM_OP_FANDCM, ASM_OP_FC,
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ASM_OP_FCHKF, ASM_OP_FCLASS, ASM_OP_FCLRF, ASM_OP_FCMP, ASM_OP_FCVT,
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ASM_OP_FETCHADD4, ASM_OP_FETCHADD8, ASM_OP_FLUSHRS, ASM_OP_FMA,
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ASM_OP_FMAX, ASM_OP_FMERGE, ASM_OP_FMIN, ASM_OP_FMIX, ASM_OP_FMS,
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ASM_OP_FNMA, ASM_OP_FOR, ASM_OP_FPACK, ASM_OP_FPAMAX, ASM_OP_FPAMIN,
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ASM_OP_FPCMP, ASM_OP_FPCVT, ASM_OP_FPMA, ASM_OP_FPMAX, ASM_OP_FPMERGE,
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ASM_OP_FPMIN, ASM_OP_FPMS, ASM_OP_FPNMA, ASM_OP_FPRCPA,
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ASM_OP_FPRSQRTA, ASM_OP_FRCPA, ASM_OP_FRSQRTA, ASM_OP_FSELECT,
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ASM_OP_FSETC, ASM_OP_FSWAP, ASM_OP_FSXT, ASM_OP_FWB, ASM_OP_FXOR,
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ASM_OP_GETF,
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ASM_OP_INVALA, ASM_OP_ITC, ASM_OP_ITR,
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ASM_OP_LD1, ASM_OP_LD16, ASM_OP_LD2, ASM_OP_LD4, ASM_OP_LD8,
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ASM_OP_LDF, ASM_OP_LDF8, ASM_OP_LDFD, ASM_OP_LDFE, ASM_OP_LDFP8,
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ASM_OP_LDFPD, ASM_OP_LDFPS, ASM_OP_LDFS, ASM_OP_LFETCH, ASM_OP_LOADRS,
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ASM_OP_MF, ASM_OP_MIX1, ASM_OP_MIX2, ASM_OP_MIX4, ASM_OP_MOV,
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ASM_OP_MOVL, ASM_OP_MUX1, ASM_OP_MUX2,
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ASM_OP_NOP,
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ASM_OP_OR,
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ASM_OP_PACK2, ASM_OP_PACK4, ASM_OP_PADD1, ASM_OP_PADD2, ASM_OP_PADD4,
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ASM_OP_PAVG1, ASM_OP_PAVG2, ASM_OP_PAVGSUB1, ASM_OP_PAVGSUB2,
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ASM_OP_PCMP1, ASM_OP_PCMP2, ASM_OP_PCMP4, ASM_OP_PMAX1, ASM_OP_PMAX2,
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ASM_OP_PMIN1, ASM_OP_PMIN2, ASM_OP_PMPY2, ASM_OP_PMPYSHR2,
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ASM_OP_POPCNT, ASM_OP_PROBE, ASM_OP_PSAD1, ASM_OP_PSHL2, ASM_OP_PSHL4,
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ASM_OP_PSHLADD2, ASM_OP_PSHR2, ASM_OP_PSHR4, ASM_OP_PSHRADD2,
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ASM_OP_PSUB1, ASM_OP_PSUB2, ASM_OP_PSUB4, ASM_OP_PTC, ASM_OP_PTR,
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ASM_OP_RFI, ASM_OP_RSM, ASM_OP_RUM,
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ASM_OP_SETF, ASM_OP_SHL, ASM_OP_SHLADD, ASM_OP_SHLADDP4, ASM_OP_SHR,
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ASM_OP_SHRP, ASM_OP_SRLZ, ASM_OP_SSM, ASM_OP_ST1, ASM_OP_ST16,
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ASM_OP_ST2, ASM_OP_ST4, ASM_OP_ST8, ASM_OP_STF, ASM_OP_STF8,
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ASM_OP_STFD, ASM_OP_STFE, ASM_OP_STFS, ASM_OP_SUB, ASM_OP_SUM,
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ASM_OP_SXT1, ASM_OP_SXT2, ASM_OP_SXT4, ASM_OP_SYNC,
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ASM_OP_TAK, ASM_OP_TBIT, ASM_OP_THASH, ASM_OP_TNAT, ASM_OP_TPA,
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ASM_OP_TTAG,
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ASM_OP_UNPACK1, ASM_OP_UNPACK2, ASM_OP_UNPACK4,
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ASM_OP_XCHG1, ASM_OP_XCHG2, ASM_OP_XCHG4, ASM_OP_XCHG8, ASM_OP_XMA,
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ASM_OP_XOR,
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ASM_OP_ZXT1, ASM_OP_ZXT2, ASM_OP_ZXT4,
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/* Additional opcodes used only internally. */
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ASM_ADDITIONAL_OPCODES
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};
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/* Instruction. */
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struct asm_inst {
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uint64_t i_bits;
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struct asm_oper i_oper[7];
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struct asm_cmpltr i_cmpltr[5];
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enum asm_fmt i_format;
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enum asm_op i_op;
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int i_ncmpltrs;
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int i_srcidx;
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};
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struct asm_bundle {
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const char *b_templ;
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struct asm_inst b_inst[3];
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};
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/* Functional units. */
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enum asm_unit {
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ASM_UNIT_NONE,
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ASM_UNIT_A = 0x0100, /* A unit. */
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ASM_UNIT_B = 0x0200, /* B unit. */
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ASM_UNIT_F = 0x0300, /* F unit. */
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ASM_UNIT_I = 0x0400, /* I unit. */
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ASM_UNIT_M = 0x0500, /* M unit. */
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ASM_UNIT_X = 0x0600 /* X unit. */
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};
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#ifdef _DISASM_INT_H_
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int asm_extract(enum asm_op, enum asm_fmt, uint64_t, struct asm_bundle *, int);
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#endif
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int asm_decode(uint64_t, struct asm_bundle *);
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void asm_completer(const struct asm_cmpltr *, char *);
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void asm_mnemonic(const enum asm_op, char *);
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void asm_operand(const struct asm_oper *, char *, uint64_t);
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void asm_print_bundle(const struct asm_bundle *, uint64_t);
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void asm_print_inst(const struct asm_bundle *, int, uint64_t);
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#endif /* _DISASM_H_ */
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